Sebastien Bourdeauducq d2491828a4 csr/SRAM: prefix page register with memory name		2013-03-01 12:06:12 +01:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
csr.py	csr/SRAM: prefix page register with memory name	2013-03-01 12:06:12 +01:00
dfi.py	Remove Constant	2012-11-28 23:18:43 +01:00
memory.py	bus: memory initiator	2012-11-23 16:22:50 +01:00
simple.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
transactions.py	bus/transactions: add busname parameter	2012-11-17 19:36:08 +01:00
wishbone.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
wishbone2asmi.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
wishbone2csr.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00