litex/miscope
Florent Kermarrec cd51e78f54 storage: use SyncFIFOBuffered to implement fifo in block ram 2014-08-02 19:12:03 +02:00
..
host host: add support for various csr_data width (8 & 32 tested, but should work with others) 2014-06-26 13:22:21 +02:00
__init__.py - reworking WIP 2013-02-22 16:40:49 +01:00
miio.py simplify and clean up 2014-05-20 09:56:35 +02:00
mila.py mila: add input pipe to ease timing 2014-05-24 09:23:16 +02:00
std.py simplify and clean up 2014-05-20 09:56:35 +02:00
storage.py storage: use SyncFIFOBuffered to implement fifo in block ram 2014-08-02 19:12:03 +02:00
trigger.py simplify and clean up 2014-05-20 09:56:35 +02:00
uart2wishbone.py uart2wishbone: add default baudrate 2014-06-05 15:13:20 +02:00