Sebastien Bourdeauducq c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" ... This reverts commit f03aa76292.		2015-03-30 19:41:16 +08:00
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altera	mibuild/altera: use new Toolchain/Platform architecture	2015-03-16 21:07:55 +01:00
lattice	mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)	2015-03-18 18:54:22 +01:00
platforms	mibuild/platforms: fix minispartan6	2015-03-30 11:42:14 +02:00
sim	mibuild/sim: use the same architecture we use for others backends	2015-03-27 14:14:49 +01:00
xilinx	platforms/kc705: add iMPACT programmer	2015-03-29 12:15:39 +02:00
__init__.py	merge Mibuild into Migen	2013-11-23 10:45:15 +01:00
generic_platform.py	Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"	2015-03-30 19:41:16 +08:00
generic_programmer.py	mibuild: better file organization (create directory for each vendor and move programmers in it)	2015-02-26 12:25:59 +01:00
tools.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00