1ce48a973b
The implementation was causing regressions on actual designs, rework done: - Only keep a common iteration loop as before. - Add iteration on CLKO dividers (to fall in the VCO range). - Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it. - If no feedback clock has been found: create it (if at least one free output available, if not raise an error). |
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.. | ||
__init__.py | ||
test_axi.py | ||
test_axi_lite.py | ||
test_bitbang.py | ||
test_clock.py | ||
test_code_8b10b.py | ||
test_csr.py | ||
test_ecc.py | ||
test_emif.py | ||
test_gearbox.py | ||
test_i2s.py | ||
test_icap.py | ||
test_packet.py | ||
test_prbs.py | ||
test_spi.py | ||
test_spi_opi.py | ||
test_stream.py | ||
test_timer.py | ||
test_wishbone.py |