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litex/examples/basic
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Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 		2013-05-28 16:11:34 +02:00
..
arrays.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
complex.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
fsm.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
graycounter.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
local_cd.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
memory.py Make memory ports part of specials 2013-05-28 16:11:34 +02:00
namer.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
psync.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
record.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
simple_gpio.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
tristate.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
two_dividers.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00