25 lines
1.1 KiB
Plaintext
25 lines
1.1 KiB
Plaintext
[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
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path = litex/soc/cores/cpu/lm32/verilog/submodule
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url = https://github.com/m-labs/lm32.git
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[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
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path = litex/soc/cores/cpu/mor1kx/verilog
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url = https://github.com/openrisc/mor1kx.git
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[submodule "litex/soc/software/compiler_rt"]
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path = litex/soc/software/compiler_rt
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url = http://llvm.org/git/compiler-rt.git
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[submodule "litex/soc/cores/cpu/picorv32/verilog"]
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path = litex/soc/cores/cpu/picorv32/verilog
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url = https://github.com/cliffordwolf/picorv32
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[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
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path = litex/build/sim/core/modules/ethernet/tapcfg
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url = https://github.com/enjoy-digital/tapcfg
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[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
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path = litex/soc/cores/cpu/vexriscv/verilog
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url = https://github.com/enjoy-digital/VexRiscv-verilog.git
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[submodule "litex/soc/cores/cpu/minerva/verilog"]
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path = litex/soc/cores/cpu/minerva/verilog
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url = http://github.com/enjoy-digital/minerva-verilog
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[submodule "litex/soc/cores/cpu/rocket/verilog"]
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path = litex/soc/cores/cpu/rocket/verilog
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url = https://github.com/gsomlo/rocket-litex-verilog
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