Gabriel Somlo d087e2e0af interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) ... Similarly to how CSRBank subregisters are aligned to the CPU word width (see commit f4770219f), ensure SRAM word_bits are also aligned to the CPU word width. Additionally, fix the MMPTR() macro to access CSR subregisters as CPU word (unsigned long) sized slices. This fixes the functionality of the 'ident' bios command on 64-bit CPUs (e.g., Rocket). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>		2020-01-03 16:36:42 -05:00
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cores	cpu/microwatt: reorder sources, add comments	2020-01-03 15:29:10 +01:00
integration	soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description	2020-01-02 09:41:47 +01:00
interconnect	interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)	2020-01-03 16:36:42 -05:00
software	interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)	2020-01-03 16:36:42 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00