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d09529d483
litex
/
misoclib
/
mem
/
sdram
/
frontend
History
Florent Kermarrec
6b24562eea
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00
..
__init__.py
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
2015-03-02 08:36:39 +01:00
dma_lasmi.py
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00
memtest.py
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
2015-03-02 08:36:39 +01:00
wishbone2lasmi.py
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00