70 lines
1.9 KiB
Python
70 lines
1.9 KiB
Python
from migen.bank.description import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
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from misoclib.tools.litescope.frontend.io import LiteScopeIO
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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class _CRG(Module):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class LiteScopeSoC(SoC, AutoCSR):
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csr_map = {
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"io": 16,
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"la": 17
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
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SoC.__init__(self, platform, clk_freq, self.uart2wb,
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with_cpu=False,
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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clk_in = platform.request(platform.default_clk_name)
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self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
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self.submodules.io = LiteScopeIO(8)
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for i in range(8):
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try:
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self.comb += platform.request("user_led", i).eq(self.io.o[i])
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except:
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pass
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self.submodules.counter0 = counter0 = Counter(8)
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self.submodules.counter1 = counter1 = Counter(8)
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self.comb += [
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counter0.ce.eq(1),
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If(counter0.value == 16,
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counter0.reset.eq(1),
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counter1.ce.eq(1)
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)
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]
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self.debug = (
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counter1.value
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)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_exit(self, vns):
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self.la.export(vns, "test/la.csv")
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default_subtarget = LiteScopeSoC
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