85 lines
2.4 KiB
Python
85 lines
2.4 KiB
Python
from random import Random
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bus import wishbone
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from migen.sim.generic import run_simulation
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# Our bus master.
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# Python generators let us program bus transactions in an elegant sequential style.
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def my_generator():
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prng = Random(92837)
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# Write to the first addresses.
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for x in range(10):
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t = TWrite(x, 2*x)
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yield t
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print("Wrote in " + str(t.latency) + " cycle(s)")
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# Insert some dead cycles to simulate bus inactivity.
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Read from the first addresses.
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for x in range(10):
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t = TRead(x)
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yield t
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print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Our bus slave.
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class MyModelWB(wishbone.TargetModel):
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def __init__(self):
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self.prng = Random(763627)
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def read(self, address):
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return address + 4
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def can_ack(self, bus):
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# Simulate variable latency.
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return self.prng.randrange(0, 2)
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class TB(Module):
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def __init__(self):
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# The "wishbone.Initiator" library component runs our generator
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# and manipulates the bus signals accordingly.
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self.submodules.master = wishbone.Initiator(my_generator())
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# The "wishbone.Target" library component examines the bus signals
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# and calls into our model object.
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self.submodules.slave = wishbone.Target(MyModelWB())
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# The "wishbone.Tap" library component examines the bus at the slave port
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# and displays the transactions on the console (<TRead...>/<TWrite...>).
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self.submodules.tap = wishbone.Tap(self.slave.bus)
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# Connect the master to the slave.
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self.submodules.intercon = wishbone.InterconnectPointToPoint(self.master.bus, self.slave.bus)
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if __name__ == "__main__":
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run_simulation(TB())
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# Output:
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# <TWrite adr:0x0 dat:0x0>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x1 dat:0x2>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x2 dat:0x4>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x3 dat:0x6>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x4 dat:0x8>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x5 dat:0xa>
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# Wrote in 2 cycle(s)
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# ...
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# <TRead adr:0x0 dat:0x4>
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# Read 4 in 2 cycle(s)
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# <TRead adr:0x1 dat:0x5>
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# Read 5 in 2 cycle(s)
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# <TRead adr:0x2 dat:0x6>
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# Read 6 in 1 cycle(s)
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# <TRead adr:0x3 dat:0x7>
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# Read 7 in 1 cycle(s)
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# ...
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