40 lines
1.0 KiB
Verilog
40 lines
1.0 KiB
Verilog
`ifdef LM32_CONFIG_V
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`else
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`define LM32_CONFIG_V
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`define CFG_EBA_RESET 32'h00860000
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`define CFG_DEBA_RESET 32'h10000000
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`define CFG_PL_MULTIPLY_ENABLED
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`define CFG_PL_BARREL_SHIFT_ENABLED
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`define CFG_SIGN_EXTEND_ENABLED
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`define CFG_MC_DIVIDE_ENABLED
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`define CFG_EBR_POSEDGE_REGISTER_FILE
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`define CFG_ICACHE_ENABLED
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`define CFG_ICACHE_ASSOCIATIVITY 1
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`define CFG_ICACHE_SETS 256
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`define CFG_ICACHE_BYTES_PER_LINE 16
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`define CFG_ICACHE_BASE_ADDRESS 32'h0
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`define CFG_ICACHE_LIMIT 32'h7fffffff
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`define CFG_DCACHE_ENABLED
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`define CFG_DCACHE_ASSOCIATIVITY 1
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`define CFG_DCACHE_SETS 256
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`define CFG_DCACHE_BYTES_PER_LINE 16
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`define CFG_DCACHE_BASE_ADDRESS 32'h0
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`define CFG_DCACHE_LIMIT 32'h7fffffff
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// Enable Debugging
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//`define CFG_JTAG_ENABLED
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//`define CFG_JTAG_UART_ENABLED
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//`define CFG_DEBUG_ENABLED
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//`define CFG_HW_DEBUG_ENABLED
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//`define CFG_ROM_DEBUG_ENABLED
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//`define CFG_BREAKPOINTS 32'h4
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//`define CFG_WATCHPOINTS 32'h4
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//`define CFG_EXTERNAL_BREAK_ENABLED
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//`define CFG_GDBSTUB_ENABLED
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`endif
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