131 lines
3.0 KiB
Python
131 lines
3.0 KiB
Python
from lib.sata.common import *
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from lib.sata.link.scrambler import Scrambler
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from migen.bank.description import *
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class SATABIST(Module):
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def __init__(self, sata_con):
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self.write = Signal()
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self.read = Signal()
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self.sector = Signal(48)
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self.count = Signal(16)
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self.loops = Signal(8)
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self.done = Signal()
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self.errors = Signal(32)
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###
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sink = sata_con.source
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source = sata_con.sink
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self.counter = counter = Counter(bits_sign=32)
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self.loops_counter = loops_counter = Counter(bits_sign=8)
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self.error_counter = Counter(self.errors, bits_sign=32)
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self.scrambler = scrambler = InsertReset(Scrambler())
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self.comb += [
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scrambler.reset.eq(counter.reset),
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scrambler.ce.eq(counter.ce)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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loops_counter.reset.eq(1),
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If(self.write,
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self.error_counter.reset.eq(1),
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NextState("SEND_WRITE_CMD_AND_DATA")
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).Elif(self.read,
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self.error_counter.reset.eq(1),
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NextState("SEND_READ_CMD")
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)
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)
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == (logical_sector_size//4*self.count)-1),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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source.data.eq(scrambler.value),
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If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
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NextState("WAIT_WRITE_ACK")
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)
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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sink.ack.eq(1),
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If(sink.stb,
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loops_counter.ce.eq(1),
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If(loops_counter.value == (self.loops-1),
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NextState("IDLE")
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).Else(
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counter.reset.eq(1),
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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)
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fsm.act("SEND_READ_CMD",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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If(source.ack,
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counter.reset.eq(1),
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NextState("WAIT_READ_ACK")
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)
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)
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fsm.act("WAIT_READ_ACK",
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If(sink.stb & sink.read,
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NextState("RECEIVE_READ_DATA")
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)
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)
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fsm.act("RECEIVE_READ_DATA",
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sink.ack.eq(1),
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != scrambler.value,
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self.error_counter.ce.eq(1)
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),
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If(sink.eop,
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If(sink.last,
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loops_counter.ce.eq(1),
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If(loops_counter.value == (self.loops-1),
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NextState("IDLE")
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).Else(
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NextState("SEND_READ_CMD")
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)
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).Else(
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NextState("WAIT_READ_ACK")
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)
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)
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)
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)
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class SATABISTControl(Module, AutoCSR):
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def __init__(self, sata_bist):
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self._write = CSR()
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self._read = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(16)
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self._loops = CSRStorage(8)
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self._done = CSRStatus()
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self._errors = CSRStatus(32)
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self.comb += [
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sata_bist.write.eq(self._write.r & self._write.re),
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sata_bist.read.eq(self._read.r & self._read.re),
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sata_bist.sector.eq(self._sector.storage),
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sata_bist.count.eq(self._count.storage),
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sata_bist.loops.eq(self._loops.storage),
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self._done.status.eq(sata_bist.done),
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self._errors.status.eq(sata_bist.errors)
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]
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