244 lines
11 KiB
Python
244 lines
11 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import SoCRegion
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# TestWishbone -------------------------------------------------------------------------------------
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class TestWishbone(unittest.TestCase):
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def test_upconverter_16_32(self):
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def generator(dut):
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yield from dut.wb16.write(0x0000, 0x1234)
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yield from dut.wb16.write(0x0001, 0x5678)
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yield from dut.wb16.write(0x0002, 0xdead)
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yield from dut.wb16.write(0x0003, 0xbeef)
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self.assertEqual((yield from dut.wb16.read(0x0000)), 0x1234)
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self.assertEqual((yield from dut.wb16.read(0x0001)), 0x5678)
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self.assertEqual((yield from dut.wb16.read(0x0002)), 0xdead)
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self.assertEqual((yield from dut.wb16.read(0x0003)), 0xbeef)
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class DUT(LiteXModule):
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def __init__(self):
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self.wb16 = wishbone.Interface(data_width=16, address_width=32, addressing="word")
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wb32 = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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up_converter = wishbone.UpConverter(self.wb16, wb32)
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self.submodules += up_converter
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wishbone_mem = wishbone.SRAM(32, bus=wb32)
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut))
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def test_converter_32_64_32(self):
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def generator(dut):
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yield from dut.wb32.write(0x0000, 0x12345678)
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yield from dut.wb32.write(0x0001, 0xdeadbeef)
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self.assertEqual((yield from dut.wb32.read(0x0000)), 0x12345678)
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self.assertEqual((yield from dut.wb32.read(0x0001)), 0xdeadbeef)
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class DUT(LiteXModule):
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def __init__(self):
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self.wb32 = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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wb64 = wishbone.Interface(data_width=64, address_width=32, addressing="word")
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wb32 = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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up_converter = wishbone.UpConverter(self.wb32, wb64)
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down_converter = wishbone.DownConverter(wb64, wb32)
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self.submodules += up_converter, down_converter
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wishbone_mem = wishbone.SRAM(32, bus=wb32)
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut))
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def test_sram_burst(self):
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def generator(dut):
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yield from dut.wb.write(0x0000, 0x01234567, cti=wishbone.CTI_BURST_INCREMENTING)
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yield from dut.wb.write(0x0001, 0x89abcdef, cti=wishbone.CTI_BURST_INCREMENTING)
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yield from dut.wb.write(0x0002, 0xdeadbeef, cti=wishbone.CTI_BURST_INCREMENTING)
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yield from dut.wb.write(0x0003, 0xc0ffee00, cti=wishbone.CTI_BURST_END)
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self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_INCREMENTING)), 0x01234567)
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self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_INCREMENTING)), 0x89abcdef)
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self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_INCREMENTING)), 0xdeadbeef)
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self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_END)), 0xc0ffee00)
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class DUT(LiteXModule):
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def __init__(self):
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self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
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wishbone_mem = wishbone.SRAM(32, bus=self.wb)
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut))
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def test_sram_burst_wrap(self):
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def generator(dut):
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bte = 0b01
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yield from dut.wb.write(0x0001, 0x01234567, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
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yield from dut.wb.write(0x0002, 0x89abcdef, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
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yield from dut.wb.write(0x0003, 0xdeadbeef, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
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yield from dut.wb.write(0x0000, 0xc0ffee00, cti=wishbone.CTI_BURST_END, bte=bte)
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self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0x01234567)
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self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0x89abcdef)
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self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0xdeadbeef)
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self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_END, bte=bte)), 0xc0ffee00)
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class DUT(LiteXModule):
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def __init__(self):
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self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
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wishbone_mem = wishbone.SRAM(32, bus=self.wb)
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut))
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def test_sram_burst_constant(self):
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def generator(dut):
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yield from dut.wb.write(0x0001, 0x01234567, cti=wishbone.CTI_BURST_CONSTANT)
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yield from dut.wb.write(0x0002, 0x89abcdef, cti=wishbone.CTI_BURST_CONSTANT)
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yield from dut.wb.write(0x0003, 0xdeadbeef, cti=wishbone.CTI_BURST_CONSTANT)
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yield from dut.wb.write(0x0000, 0xc0ffee00, cti=wishbone.CTI_BURST_END)
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self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_CONSTANT)), 0x01234567)
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self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_CONSTANT)), 0x89abcdef)
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self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_CONSTANT)), 0xdeadbeef)
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self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_END)), 0xc0ffee00)
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class DUT(LiteXModule):
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def __init__(self):
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self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
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wishbone_mem = wishbone.SRAM(32, bus=self.wb)
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut))
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def test_origin_remap(self):
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def generator(dut):
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yield from dut.master.write(0x0000_0000, 0)
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yield from dut.master.write(0x0000_0004, 0)
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yield from dut.master.write(0x0000_0008, 0)
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yield from dut.master.write(0x0000_000c, 0)
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yield from dut.master.write(0x1000_0000, 0)
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yield from dut.master.write(0x1000_0004, 0)
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yield from dut.master.write(0x1000_0008, 0)
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yield from dut.master.write(0x1000_000c, 0)
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def checker(dut):
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yield dut.slave.ack.eq(1)
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while (yield dut.slave.stb) == 0:
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0000)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0004)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0008)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_000c)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0000)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0004)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_0008)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0001_000c)
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print((yield dut.slave.adr))
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class DUT(LiteXModule):
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def __init__(self):
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self.master = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.remapper = wishbone.Remapper(self.master, self.slave,
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origin = 0x0001_0000,
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size = 0x1000_0000,
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)
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dut = DUT()
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run_simulation(dut, [generator(dut), checker(dut)])
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def test_region_remap(self):
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def generator(dut):
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yield from dut.master.write(0x0000_0000, 0)
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yield from dut.master.write(0x0001_0004, 0)
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yield from dut.master.write(0x0002_0008, 0)
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yield from dut.master.write(0x0003_000c, 0)
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def checker(dut):
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yield dut.slave.ack.eq(1)
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while (yield dut.slave.stb) == 0:
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yield
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self.assertEqual((yield dut.slave.adr), 0x0000_0000)
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yield
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self.assertEqual((yield dut.slave.adr), 0x1000_0004)
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yield
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self.assertEqual((yield dut.slave.adr), 0x2000_0008)
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yield
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self.assertEqual((yield dut.slave.adr), 0x3000_000c)
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yield
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class DUT(LiteXModule):
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def __init__(self):
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self.master = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.remapper = wishbone.Remapper(self.master, self.slave,
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src_regions = [
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SoCRegion(origin=0x0000_0000, size=0x1000),
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SoCRegion(origin=0x0001_0000, size=0x1000),
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SoCRegion(origin=0x0002_0000, size=0x1000),
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SoCRegion(origin=0x0003_0000, size=0x1000),
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],
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dst_regions = [
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SoCRegion(origin=0x0000_0000, size=0x1000),
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SoCRegion(origin=0x1000_0000, size=0x1000),
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SoCRegion(origin=0x2000_0000, size=0x1000),
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SoCRegion(origin=0x3000_0000, size=0x1000),
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]
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)
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dut = DUT()
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run_simulation(dut, [generator(dut), checker(dut)], vcd_name="sim.vcd")
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def test_origin_region_remap(self):
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def generator(dut):
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yield from dut.master.write(0x0000_0000, 0)
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yield from dut.master.write(0x0002_0000, 0)
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#yield from dut.master.write(0x0001_0004, 0)
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#yield from dut.master.write(0x0002_0008, 0)
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#yield from dut.master.write(0x0003_000c, 0)
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def checker(dut):
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yield dut.slave.ack.eq(1)
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while (yield dut.slave.stb) == 0:
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yield
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self.assertEqual((yield dut.slave.adr), 0x1000_0000)
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yield
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self.assertEqual((yield dut.slave.adr), 0x0003_0000)
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yield
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for i in range(128):
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yield
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class DUT(LiteXModule):
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def __init__(self):
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self.master = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.remapper = wishbone.Remapper(self.master, self.slave,
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origin = 0x1_0000,
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size = 0x8_0000,
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src_regions = [
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SoCRegion(origin=0x0001_0000, size=0x1_0000),
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],
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dst_regions = [
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SoCRegion(origin=0x1000_0000, size=0x1_0000),
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]
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)
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dut = DUT()
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run_simulation(dut, [generator(dut), checker(dut)], vcd_name="sim.vcd")
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