190 lines
4.4 KiB
Python
190 lines
4.4 KiB
Python
################################################################################
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# _____ _ ____ _ _ _ _
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# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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# | __| | | | . | | | | | | | . | | _| .'| |
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# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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# |___| |___| |___|
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#
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# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# migScope Example on De1 Board
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# ----------------------------------
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################################################################################
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#
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# In this example signals are generated in the FPGA.
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# We will use migScope to record those signals and visualize them.
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#
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# Example architecture:
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# ----------------------
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# migScope Config --> Python Client (Host) --> Vcd Output
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# & Trig |
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# Arduino (Uart<-->Spi Bridge)
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# |
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# De1
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# |
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# +--------------------+-----------------------+
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# migIo Signal Generator migLa
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# Control of Signal Ramp, Sinus, Logic Analyzer
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# generator Square, ...
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###############################################################################
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder, migIo
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import spi2Csr
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from timings import *
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from constraints import Constraints
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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#Timings Param
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clk_freq = 50*MHz
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clk_period_ns = clk_freq*ns
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n = t2n(clk_period_ns)
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 4096
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# Csr Addr
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MIGIO_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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#==============================================================================
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# M I S C O P E E X A M P L E
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#==============================================================================
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def get():
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# migIo
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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migIo0.bank.interface,
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trigger0.bank.interface,
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recorder0.bank.interface
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])
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comb = []
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sync = []
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#
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# Signal Generator
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#
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# Counter
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cnt_gen = Signal(BV(8))
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sync += [
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cnt_gen.eq(cnt_gen+1)
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]
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# Square
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square_gen = Signal(BV(8))
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sync += [
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If(cnt_gen[7],
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square_gen.eq(255)
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).Else(
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square_gen.eq(0)
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)
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]
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# Signal Selection
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sig_gen = Signal(BV(8))
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comb += [
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If(migIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(migIo0.o == 1,
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sig_gen.eq(square_gen)
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).Else(
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sig_gen.eq(0)
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)
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]
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ramp_gen = Signal(BV(8))
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sync += [
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ramp_gen.eq(ramp_gen+1)
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]
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square_gen = Signal(BV(8))
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sync += [
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ramp_gen.eq(ramp_gen+1)
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]
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#comb += [sig_gen.eq(migIo0.o)]
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# Led
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led0 = Signal(BV(8))
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comb += [led0.eq(migIo0.o[:8])]
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#Switch
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sw0 = Signal(BV(8))
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comb += [migIo0.i.eq(sw0)]
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# Dat / Trig Bus
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comb += [
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trigger0.in_trig.eq(sig_gen),
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trigger0.in_dat.eq(sig_gen)
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]
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# Trigger --> Recorder
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comb += [
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recorder0.trig_dat.eq(trigger0.dat),
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recorder0.trig_hit.eq(trigger0.hit)
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]
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# HouseKeeping
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in_clk = Signal()
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in_rst_n = Signal()
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in_rst = Signal()
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comb += [
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in_rst.eq(~in_rst_n)
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]
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frag = autofragment.from_local()
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frag += Fragment(sync=sync,comb=comb)
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cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="de1",
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clk_signal = in_clk,
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rst_signal = in_rst,
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return_ns=True)
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src_qsf = cst.get_qsf(vns)
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return (src_verilog, src_qsf) |