9 lines
302 B
Python
9 lines
302 B
Python
from migen.fhdl import verilog
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from migen.corelogic import roundrobin, divider
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r = roundrobin.Inst(5)
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d = divider.Inst(16)
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frag = r.get_fragment() + d.get_fragment()
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o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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print(o)
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