litex/misoclib/soc
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
..
__init__.py rename sdram mapping to main_ram 2015-03-21 21:01:46 +01:00
cpuif.py cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
sdram.py sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00