42 lines
1.4 KiB
Python
42 lines
1.4 KiB
Python
from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.io import *
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from mibuild.generic_platform import GenericPlatform
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from mibuild.xilinx import common, vivado, ise
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class XilinxPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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def __init__(self, *args, toolchain="ise", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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if toolchain == "ise":
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self.toolchain = ise.XilinxISEToolchain()
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elif toolchain == "vivado":
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self.toolchain = vivado.XilinxVivadoToolchain()
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else:
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raise ValueError("Unknown toolchain")
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = {
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NoRetiming: common.XilinxNoRetiming,
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MultiReg: common.XilinxMultiReg,
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AsyncResetSynchronizer: common.XilinxAsyncResetSynchronizer,
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DifferentialInput: common.XilinxDifferentialInput,
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DifferentialOutput: common.XilinxDifferentialOutput,
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}
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
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def get_edif(self, fragment, **kwargs):
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return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period)
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