101 lines
4.2 KiB
Python
101 lines
4.2 KiB
Python
from litex.gen import *
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from litex.gen.genlib.record import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR
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from litex.soc.integration.soc_core import *
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from litedram.frontend import crossbar
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from litedram.frontend.bridge import LiteDRAMWishboneBridge
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from litedram import dfii, core
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__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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class ControllerInjector(Module, AutoCSR):
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def __init__(self, phy, geom_settings, timing_settings, **kwargs):
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self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
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phy.settings.dfi_databits, phy.settings.nphases)
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self.comb += self.dfii.master.connect(phy.dfi)
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self.submodules.controller = controller = core.LiteDRAMController(phy.settings,
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geom_settings,
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timing_settings,
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**kwargs)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
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class SoCSDRAM(SoCCore):
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csr_map = {
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"sdram": 8,
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"l2_cache": 9
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
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SoCCore.__init__(self, platform, clk_freq, **kwargs)
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self.l2_size = l2_size
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self._sdram_phy = []
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self._wb_sdram_ifs = []
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self._wb_sdram = wishbone.Interface()
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def add_wb_sdram_if(self, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_sdram_ifs.append(interface)
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def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
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assert not self._sdram_phy
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self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
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self.submodules.sdram = ControllerInjector(phy,
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geom_settings,
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timing_settings,
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**kwargs)
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dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
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sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
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main_ram_size = 2**(geom_settings.bankbits +
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geom_settings.rowbits +
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geom_settings.colbits)*sdram_width//8
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# TODO: modify mem_map to allow larger memories.
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main_ram_size = min(main_ram_size, 256*1024*1024)
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self.add_constant("L2_SIZE", self.l2_size)
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# add a Wishbone interface to the DRAM
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wb_sdram = wishbone.Interface()
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self.add_wb_sdram_if(wb_sdram)
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self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
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if self.l2_size:
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port = self.sdram.crossbar.get_port()
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l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.dw))
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from litex.build.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from litex.gen.fhdl.simplify import FullMemoryWE
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.l2_cache = l2_cache
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self.submodules.wishbone_bridge = LiteDRAMWishboneBridge(self.l2_cache.slave, port)
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def do_finalize(self):
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if not self.integrated_main_ram_size:
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if not self._sdram_phy:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram()")
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# arbitrate wishbone interfaces to the DRAM
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self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
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self._wb_sdram)
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SoCCore.do_finalize(self)
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soc_sdram_args = soc_core_args
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soc_sdram_argdict = soc_core_argdict
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