litex/litex/soc/interconnect
2020-04-14 17:35:19 +02:00
..
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
avalon.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
axi.py Fix copyrights 2020-03-05 17:44:10 +01:00
csr.py interconnect/csr: add reset_less parameter. 2020-04-06 13:15:08 +02:00
csr_bus.py interconnect/csr, wishbone: use reset_less on datapath signals. 2020-04-06 13:11:50 +02:00
csr_eventmanager.py csr_eventmanager: add name and description args 2019-09-19 17:23:03 +08:00
packet.py soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. 2020-01-16 09:46:54 +01:00
stream.py stream/AsyncFIFO: add default depth (useful when used for CDC). 2020-04-14 17:35:19 +02:00
stream_sim.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
wishbone.py interconnect/csr, wishbone: use reset_less on datapath signals. 2020-04-06 13:11:50 +02:00
wishbone2csr.py wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) 2019-09-24 17:55:29 +02:00
wishbonebridge.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00