litex/migen/bus
2012-11-17 19:44:25 +01:00
..
__init__.py
asmibus.py bus/asmibus: swap port position to be consistent with wishbone API 2012-11-17 19:42:39 +01:00
csr.py bus/csr: allow specifying existing interface 2012-11-17 19:44:25 +01:00
dfi.py
simple.py
transactions.py bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
wishbone.py bus/wishbone: allow specifying existing interface 2012-11-17 19:42:06 +01:00
wishbone2asmi.py bus/wishbone2asmi: fix cache tag size 2012-05-15 15:18:03 +02:00
wishbone2csr.py bus/csr: configurable data width 2012-08-26 21:19:34 +02:00