23 lines
530 B
Python
23 lines
530 B
Python
from migen.fhdl.std import *
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from migen.sim.generic import run_simulation
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from migen.fhdl import verilog
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class SimBench(Module):
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callback = None
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def do_simulation(self, selfp):
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if self.callback is not None:
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return self.callback(self, selfp)
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class SimCase:
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TestBench = SimBench
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def setUp(self, *args, **kwargs):
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self.tb = self.TestBench(*args, **kwargs)
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def test_to_verilog(self):
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verilog.convert(self.tb)
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def run_with(self, cb, ncycles=None):
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self.tb.callback = cb
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run_simulation(self.tb, ncycles=ncycles)
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