Sebastien Bourdeauducq d8e478efee Replace Signal(bits_for(... with Signal(max=...		2012-11-29 21:53:36 +01:00
..
actorlib	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
bank	New specification for width and signedness	2012-11-29 21:22:38 +01:00
bus	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
corelogic	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
fhdl	New specification for width and signedness	2012-11-29 21:22:38 +01:00
flow	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
pytholite	New specification for width and signedness	2012-11-29 21:22:38 +01:00
sim	New specification for width and signedness	2012-11-29 21:22:38 +01:00
uio	pytholite/io: support memory	2012-11-23 20:36:09 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00