32 lines
976 B
Python
32 lines
976 B
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.genlib.record import Record
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from migen.flow.actor import Sink, Source
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class UART(Module, AutoCSR):
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def __init__(self, phy):
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self._rxtx = CSR(8)
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourcePulse()
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self.ev.rx = EventSourcePulse()
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self.ev.finalize()
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###
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self.sync += [
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If(self._rxtx.re,
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phy.sink.stb.eq(1),
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phy.sink.data.eq(self._rxtx.r),
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).Elif(phy.sink.ack,
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phy.sink.stb.eq(0)
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),
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If(phy.source.stb,
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self._rxtx.w.eq(phy.source.data)
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)
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]
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self.comb += [
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self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
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self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),
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phy.source.ack.eq(~self.ev.rx.pending)
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]
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