59 lines
2.4 KiB
Python
59 lines
2.4 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from misoclib.mem.sdram.phy import dfi
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class PhaseInjector(Module, AutoCSR):
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def __init__(self, phase):
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self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
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self._command_issue = CSR()
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self._address = CSRStorage(flen(phase.address))
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self._baddress = CSRStorage(flen(phase.bank))
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self._wrdata = CSRStorage(flen(phase.wrdata))
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self._rddata = CSRStatus(flen(phase.rddata))
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###
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self.comb += [
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If(self._command_issue.re,
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phase.cs_n.eq(~self._command.storage[0]),
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phase.we_n.eq(~self._command.storage[1]),
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phase.cas_n.eq(~self._command.storage[2]),
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phase.ras_n.eq(~self._command.storage[3])
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).Else(
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phase.cs_n.eq(1),
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phase.we_n.eq(1),
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phase.cas_n.eq(1),
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phase.ras_n.eq(1)
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),
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phase.address.eq(self._address.storage),
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phase.bank.eq(self._baddress.storage),
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phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
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phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
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phase.wrdata.eq(self._wrdata.storage),
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phase.wrdata_mask.eq(0)
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]
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self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
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class DFIInjector(Module, AutoCSR):
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def __init__(self, addressbits, bankbits, databits, nphases=1):
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inti = dfi.Interface(addressbits, bankbits, databits, nphases)
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self.slave = dfi.Interface(addressbits, bankbits, databits, nphases)
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self.master = dfi.Interface(addressbits, bankbits, databits, nphases)
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self._control = CSRStorage(4) # sel, cke, odt, reset_n
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for n, phase in enumerate(inti.phases):
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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###
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self.comb += If(self._control.storage[0],
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self.slave.connect(self.master)
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).Else(
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inti.connect(self.master)
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)
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self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]
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self.comb += [phase.odt.eq(self._control.storage[2]) for phase in inti.phases if hasattr(phase, "odt")]
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self.comb += [phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases if hasattr(phase, "reset_n")]
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