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270 lines
10 KiB
Python
270 lines
10 KiB
Python
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2016-2019 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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"""
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CSR-2 bus
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=========
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The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing
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the configuration and status registers of cores from software.
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"""
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from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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from migen.util.misc import xdir
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from litex.soc.interconnect import csr
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from litex.soc.interconnect.csr import CSRStorage
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# CSR Definition -----------------------------------------------------------------------------------
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_layout = [
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("adr", "address_width", DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=8, address_width=14, alignment=32):
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self.data_width = data_width
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self.address_width = address_width
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self.alignment = alignment
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Record.__init__(self, set_layout_parameters(_layout,
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data_width = data_width,
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address_width = address_width))
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self.adr.reset_less = True
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self.dat_w.reset_less = True
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self.dat_r.reset_less = True
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@classmethod
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def like(self, other):
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return Interface(len(other.dat_w),
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len(other.adr))
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def write(self, adr, dat):
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yield self.adr.eq(adr)
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yield self.dat_w.eq(dat)
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yield self.we.eq(1)
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yield
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yield self.we.eq(0)
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def read(self, adr):
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yield self.adr.eq(adr)
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yield
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yield
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return (yield self.dat_r)
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# CSR Interconnect ---------------------------------------------------------------------------------
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class Interconnect(Module):
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def __init__(self, master, slaves):
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self.comb += master.connect(*slaves)
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class InterconnectShared(Module):
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def __init__(self, masters, slaves):
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intermediate = Interface.like(masters[0])
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self.comb += [
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intermediate.adr.eq(reduce(or_, [masters[i].adr for i in range(len(masters))])),
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intermediate.we.eq(reduce(or_, [masters[i].we for i in range(len(masters))])),
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intermediate.dat_w.eq(reduce(or_, [masters[i].dat_w for i in range(len(masters))]))
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]
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for i in range(len(masters)):
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self.comb += masters[i].dat_r.eq(intermediate.dat_r)
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self.comb += intermediate.connect(*slaves)
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# CSR SRAM -----------------------------------------------------------------------------------------
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class SRAM(Module):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800, soc_bus_data_width=32):
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if bus is None:
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bus = Interface()
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self.bus = bus
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aligned_paging = paging//(soc_bus_data_width//8)
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data_width = len(self.bus.dat_w)
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if isinstance(mem_or_size, Memory):
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mem = mem_or_size
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else:
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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mem_size = int(mem.width*mem.depth/8)
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if mem_size > aligned_paging:
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print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
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aligned_paging, mem_size))
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
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if page_bits:
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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else:
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self._page = None
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if read_only is None:
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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# # #
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port = mem.get_port(write_capable=not read_only)
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self.specials += mem, port
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sel = Signal()
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sel_r = Signal()
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self.sync += sel_r.eq(sel)
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self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
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if bus.alignment == 64:
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self.comb += If(self.bus.adr[0], sel.eq(0))
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adr_shift = log2_int(bus.alignment//32)
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if word_bits:
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word_index = Signal(word_bits, reset_less=True)
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word_expanded = Signal(csrw_per_memw*data_width)
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self.sync += word_index.eq(self.bus.adr[adr_shift:adr_shift+word_bits])
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self.comb += [
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word_expanded.eq(port.dat_r),
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If(sel_r,
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chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
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)
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]
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if not read_only:
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wregs = []
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for i in range(csrw_per_memw-1):
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wreg = Signal(data_width, reset_less=True)
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self.sync += If(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == i), wreg.eq(self.bus.dat_w))
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wregs.append(wreg)
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memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
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self.comb += [
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port.we.eq(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == csrw_per_memw - 1)),
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port.dat_w.eq(Cat(*memword_chunks))
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]
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else:
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self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
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if not read_only:
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self.comb += [
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port.we.eq(sel & self.bus.we),
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port.dat_w.eq(self.bus.dat_w)
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]
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if self._page is None:
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self.comb += port.adr.eq(self.bus.adr[adr_shift+word_bits:adr_shift+word_bits+len(port.adr)])
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else:
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pv = self._page.storage
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self.comb += port.adr.eq(Cat(self.bus.adr[adr_shift+word_bits:adr_shift+word_bits+len(port.adr)-len(pv)], pv))
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def get_csrs(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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# CSR Bank -----------------------------------------------------------------------------------------
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class CSRBank(csr.GenericBank):
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def __init__(self, description, address=0, bus=None, paging=0x800, soc_bus_data_width=32):
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if bus is None:
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bus = Interface()
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self.bus = bus
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aligned_paging = paging//(soc_bus_data_width//8)
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# # #
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csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
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sel = Signal()
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self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
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if bus.alignment == 64:
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self.comb += If(self.bus.adr[0], sel.eq(0))
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adr_shift = log2_int(bus.alignment//soc_bus_data_width)
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for i, c in enumerate(self.simple_csrs):
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self.comb += [
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c.r.eq(self.bus.dat_w[:c.size]),
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c.re.eq(sel & \
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self.bus.we & \
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(self.bus.adr[adr_shift:adr_shift+self.decode_bits] == i)),
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c.we.eq(sel & \
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~self.bus.we & \
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(self.bus.adr[adr_shift:adr_shift+self.decode_bits] == i)),
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]
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brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
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self.sync += [
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self.bus.dat_r.eq(0),
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If(sel, Case(self.bus.adr[adr_shift:adr_shift+self.decode_bits], brcases))
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]
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# address_map(name, memory) returns the CSR offset at which to map
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# the CSR object (register bank or memory).
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# If memory=None, the object is the register bank of object source.name.
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# Otherwise, it is a memory object belonging to source.name.
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# address_map is called exactly once for each object at each call to
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# scan(), so it can have side effects.
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class CSRBankArray(Module):
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def __init__(self, source, address_map, *ifargs, paging=0x800, soc_bus_data_width=32, **ifkwargs):
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self.source = source
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self.address_map = address_map
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self.paging = paging
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self.soc_bus_data_width = soc_bus_data_width
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self.scan(ifargs, ifkwargs)
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def scan(self, ifargs, ifkwargs):
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self.banks = []
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self.srams = []
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self.constants = []
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for name, obj in xdir(self.source, True):
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if hasattr(obj, "get_csrs"):
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csrs = obj.get_csrs()
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else:
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csrs = []
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if hasattr(obj, "get_memories"):
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memories = obj.get_memories()
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for memory in memories:
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if isinstance(memory, tuple):
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read_only, memory = memory
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else:
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read_only = False
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mapaddr = self.address_map(name, memory)
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if mapaddr is None:
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continue
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sram_bus = Interface(*ifargs, **ifkwargs)
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mmap = SRAM(memory, mapaddr,
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read_only = read_only,
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bus = sram_bus,
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paging = self.paging)
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self.submodules += mmap
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csrs += mmap.get_csrs()
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self.srams.append((name, memory, mapaddr, mmap))
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if hasattr(obj, "get_constants"):
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for constant in obj.get_constants():
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self.constants.append((name, constant))
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if csrs:
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mapaddr = self.address_map(name, None)
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if mapaddr is None:
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continue
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bank_bus = Interface(*ifargs, **ifkwargs)
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rmap = CSRBank(csrs, mapaddr,
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bus = bank_bus,
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paging = self.paging,
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soc_bus_data_width = self.soc_bus_data_width)
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self.submodules += rmap
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self.banks.append((name, csrs, mapaddr, rmap))
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def get_rmaps(self):
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return [rmap for name, csrs, mapaddr, rmap in self.banks]
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def get_mmaps(self):
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return [mmap for name, memory, mapaddr, mmap in self.srams]
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def get_buses(self):
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return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
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