Florent Kermarrec db4739df81 soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)		2019-11-08 12:55:29 +01:00
..
cores	cpu/rocket: parameterize axi interface data width	2019-11-01 08:55:27 -04:00
integration	soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)	2019-11-08 12:55:29 +01:00
interconnect	interconnect/csr_bus/SRAM: add mem_size check	2019-11-01 11:33:50 +01:00
software	Fix file names for the mor1kx processor.	2019-10-30 13:50:01 -07:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00