533 lines
28 KiB
Plaintext
533 lines
28 KiB
Plaintext
[> Changes since 2022.08
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------------------------
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[> Issues resolved
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------------------
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[> Added Features
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-----------------
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[> API changes/Deprecation
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--------------------------
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[> 2022.08, released on September 12th 2022
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-------------------------------------------
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[> Issues resolved
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------------------
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- cpu/vexriscv: Fix compilation with new binutils.
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- soc/LiteXSocArgumentParser: Fix --cpu-type parsing.
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- litex_sim: Fix --with-ethernet.
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- liblitesdcard: Fix SDCard initialization corner cases.
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- liblitedram: Enable sdram_init/mr_write for SDRAM.
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- export/get_memory_x: Replace SPIFlash with ROM.
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- soc/cores/video: Fix operation with some monitors (set data to 0 during blanking).
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- tools/remote/comm_usb: Fix multi-word reads/writes.
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- build/lattice/oxide: Fix ES posfix on device name.
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- interconnect/axi: Fix AXIArbiter corner case.
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- litex_server/client: Fix remapping over CommPCIe.
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- LitePCIe: Fix LiteUART support with multi-boards.
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[> Added Features
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-----------------
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- litex_setup: Add -tag support for install/update.
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- tools: Add initial LiteX standalone SoC generator.
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- cores/ram: Add Xilinx's FIFO_SYNC_MACRO equivalent.
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- LitePCIe: Always use 24-bit depth fields on LitePCIeBuffering to simplify software.
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- gen/fhdl: Integrate Migen namer to give us more flexibility.
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- fhdl/memory: Prefix memory files with build name to simplify reuse/integration.
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- cpu/rocket: Add more variants.
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- cores/video: Enable driving both + and - diff outs to compensate hardware issues.
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- build: Add intial OSFPGA Foedag/Raptor build backend.
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- cpu/cva5: Add initial CVA5 CPU support (ex Taiga).
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- LiteSATA: Add IRQ and Identify support.
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- clock/intel: Improve to find the best PLL config.
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- cpu/cva6: Add initial CVA6 CPU support (ex Ariane).
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- bios: Improve config flags.
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- tools: Add I2s/MMCM support to litex_json2dts_zephyr.
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- clock/gowin: Add GW2A support.
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- bios: Disable LTO (does not work in all cases, needs to be investigated).
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- CI: Test more RISC-V CPUs and OpenRisc CPUs in CI.
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- bios: Add CONFIG_NO_BOOT to allow disabling boot sequence.
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- export: Allow disabling CSR_BASE define in csr.h.
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- build/openocd: Update for compatibility with upstream OpenOCD.
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- cpu/openc906: Add initial OpenC906 support (open version of the Allwinner's D1 chip).
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- soc: Add automatic bridging between AXI <-> AXI-Lite <-> Wishbone.
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- soc: Add AXI-Full bus support.
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- interconnect: Add AXI DownConverted and Interconnect/Crossbar.
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- interconnect: Create axi directory and split code.
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- soc: Modify SoC finalization order for more flexibility.
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- soc: Add --bus-interconnect parameter to select interconect: shared/crossbar.
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- valentyusb: Package and install it with LiteX.
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- bios/mem_list: Align Mem Regions.
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- build: Introduce GenericToolchain to cleanup/simplify build backends.
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- soc/etherbone: Expose broadcast capability.
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- build/lattice: Add MCLK frequency support.
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- cpu/cva6: Add IRQ support.
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- cores/clock: Add manual placement support to ECP5PLL.
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- cores/leds: Add polarity support.
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- cpu/neorv32: Switch to new NeoRV32 LiteX Core Complex and add variants support.
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- cores/gpio: Add optional reset value.
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- litex_client: Add --host support for remote operation.
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- sim/verilator: Add jobs number support (to limit RAM usage with large SoCs/CPUs).
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- soc/SocBusHandler Add get_address_width method to simplify peripheral integration.
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- bios: Expose BIOS console parameters (to enable/disable history/autocomplete).
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- bios: Expose BIOS LTO configuration.
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- litex_json2renode: Update.
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- build: Introduce YosysNextPNRToolchain to cleanup/simplify Yosys support.
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- bios: Add buttons support/command.
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- litex_client: Add XADC/Identifier/Leds/Buttons support to GUI.
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- cpu/NaxRiscv: Update.
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- build/generic_platofrm: Add add_connector methode to allow extending connectors.
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- litex_server/client: Add initial information exchange between server/client.
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- LitePCIe: Improve 64-bit support.
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- interconnect/axi: Add missing optional signals.
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- interconnect/wishbone: Improve DownConverter efficiency.
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[> API changes/Deprecation
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--------------------------
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- LiteX-Boards : Remove short import support on platforms/targets.
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- tools: Rename litex_gen to litex_periph_gen.
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- LiteX-Boards: Only generate SoC/Software headers when --build is set
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- Symbiflow: Rename to F4PGA.
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- mkmsscimg: Rename to crcfbigen.
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[> 2022.04, released on May 3th 2022
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------------------------------------
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[> Issues resolved
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------------------
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- software/bios/mem_write: Fix write address increment.
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- software/liblitedram: Improve calibration corner case on 7-series (SDRAM_PHY_DELAY_JUMP).
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- software/liblitedram: Fix delay reconfiguration issue on ECP5/DDR3.
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- cores/jtag: Fix chain parameter on XilinxJTAG.
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- soc/arguments: Fix l2_size handling.
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- cpu/vexriscv_smp: Fix pbus_width when using direct LiteDRAM interface.
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- libbase/i2c/i2c_poll: Also check for write in i2c_scan (some chips are write only).
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- build/vivado: Fix timing constraints application on nets/ports.
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[> Added Features
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-----------------
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- litex_setup: Add minimal/standard/full install configs.
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- soc/arguments: Improve default/help, add parser groups.
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- LiteSPI/phy: Simplify integration on targets.
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- openocd/stream: Simplify ECP5 JTAG-UART/JTAGBone use.
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- tools/litex_cli: Allow passing reg name to --read/--write.
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- soc/add_spi_sdcard: Allow optional Tristate (useful on ULX3S).
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- software/bios: Add new mem_cmd memory comparison command.
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- cpu/rocket: Increase IRQ lines to 8.
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- cpu/serv: Add MDU support.
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- cpu/marocchino: Add initial support.
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- cpu/eos_s3: Add LiteX BIOS/Bare Metal software support.
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- litex_sim: Add .json support for --rom/ram/sdram-init.
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- soc/add_uart: Allow multiple UARTs in the same design.
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- cores/cpu: Add out-of-tree support.
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- build/xilinx: Add initial Yosys/NextPnr support on Artix7 (and Zynq7000 with Artix7 fabric).
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- add_source: Add optional copy to gateware directory.
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- cores/jtag: Add initial JTAG-UART/JTAGBone Altera/Intel support.
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- LiteScope: Add Samplerate support.
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- cores/bitbang: Add optional I2C initialization by CPU.
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- libliteeth/tftp: Add blocksize support an increase to 1024 bytes (allow 64MB filesize).
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- soc/add_sdram: Make AXI integration more flexible (remove some specific Rocket hardcoding).
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- cpu/neorv32: Add initial support (RV32I, VHDL converted to Verilog through GHDL-Yosys-synth).
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- cpu/naxriscv: Add initial support (RV32IMA & RV64IMA, already able to run Linux).
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- interconnect/axi: Add AXI UpConverter.
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- soc/add_sdram: Allow data_width upconversion directly on AXI (avoid switching to Wishbone).
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- bios/memtest: Optimize memspeed loop for better accuracy.
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- build/sim: Allow custom modules to be in custom path.
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- build/OpenFPGA: Add initial OpenFPGA build backend (Currently targeting SOFA chips).
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- build/efinix: Add initial MIPI TX/RX support (and test on Trion/Titanium).
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- cores/video: VTG improvements to support more Video chips.
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- cores/xadc: Improve Zynq Ultrascale+ support.
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- LiteScope: Optimize waveform upload speed.
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- LitePCIe: Add LTSSM tracer capability to debug PCIe bringup issues.
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- cores/hyperbus: Refactor core and improve performances (Automatic burst detection).
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- cores/jtag: Add Zynq UltraScale+.
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- cores/ram: Add Ultrascale+ HBM2 wrapper.
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- litex_json2renode: Improve and add support for more CPUs.
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- cores/cpu: Add initial FireV support.
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- litex_cli: Add --csr-csv support and minimal GUI (based on DearPyGui).
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- litescope_cli: Add minimal GUI (based on DearPyGui).
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- build/gowin: Add powershell support.
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- LitePCIe: Add initial 64-bit addressing support (Only for 64-bit datapath for now).
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- software/bios: Add Main RAM test (when not pre-initialized).
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- build/trellis: Enable bitstream compression on ECP5 by default.
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- soc/add_etherbone: Increase buffer_depth to 16 (to improve etherbone bursting).
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- builder: Add get_bios_filename/get_bitstream_filename methods to simplify targets.
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- cpu/vexriscv_smp: Re-integrate Linux-on-LiteX−VexRiscv specific changes/mapping.
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- tools/litex_sim: Allow RAM/SDRAM initialization from .json files (similar to hardware).
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- soc/cpu: Expose optional CPU configuration parameters to users (ex VexRiscv-SMP/NaxRiscv).
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- soc: Improve logs.
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- build/Efinix: Add Atmel programmer.
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- stream/cdc: Add optional common reset.
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- LiteDRAM: Decouple DQ/DQS widths on S7DDRPHY.
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- cores/ws2812: Improve timings at low sys_clk_freq.
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- soc/builder: Add --no-compile (similar to --no-compile-gateware --no-compile-software).
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- software/demo: Add --mem parameter to allow compilation for execution in ROM/RAM.
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- cpu/naxrsicv: Add JTAG debug support.
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- cores/usb_fifo: Re-implement FT245PHYSYnchronous.
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- cores/jtag: Add JTAGBone/JTAG-UART support on Zynq/ZynqMP.
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- interconnect/sram: Add SRAM burst support.
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- liblitesata: Improve SATA init.
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- soc/cpu: Improve command line listing.
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- soc/cores/uart: Decouple data/address width on Stream2Wishbone.
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[> API changes/Deprecation
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--------------------------
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- Fully deprecate SoCSDRAM/SPIFlash core (replaced by LiteSPI).
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- UART "bridge" name deprecated in favor of "crossover" (already supported).
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- "external" CPU class support deprecated (replaced by out-of-tree support).
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- lxterm/lxserver/lxsim short names deprecated (used long litex_xy names).
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- Deprecate JTAG-Atlantic support (Advantageously replaced by JTAG-UART).
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[> 2021.12, released on January 5th 2022
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----------------------------------------
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[> Issues resolved
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------------------
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- software/linker: Fix initialized global variables.
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- build/xilinx: Fix Ultrascale SDROutput/Input.
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- cpu/rocket/crt0.s: Fix alignements.
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- core/video: Fix missing ClockDomainsRenamer in specific DRAM's width case.
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- mor1kx: Fix --cpu-type=None --with-ethernet case.
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- build/lattice: Fix LatticeiCE40SDROutputImpl.
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- soc/interconnect/axi: Fix 4KB bursts.
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[> Added Features
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-----------------
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- integration/builder: Check if full software re-build is required when a CPU is used.
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- cores/clock: Add Gowin PLL support.
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- build/gowin: Add initial HyperRam support.
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- build/gowin: Add differential Input/Output support.
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- build/lattice: Add DDRTristate support.
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- cores/gpio: Add external Tristate support.
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- tools/json2dts: Make it more generic (now also used with OpenRisc/Mor1kx).
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- cpu/rocket: Add SMP support (up to quad-core).
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- software/bios/boot: Allow frame reception to time out (for litex_term auto-calibration).
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- tools/litex_term: Add automatic settings calibration and --safe mode.
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- build/quicklogic: Add initial support.
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- cores/icap/7-Series: Add register read capability.
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- cores/video: Add RGB565 support to VideoFrameBuffer.
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- soc: Raise custom SoCError Exception and disable traceback/exception.
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- soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness.
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- build/efinix: Add initial Trion and Titanium support.
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- fhdl/verilog: Cleanup/Simplify verilog generation.
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- fhdl/memory: Cleanup/Simplify and add support for Efinix case.
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- cpu/ibex: Add interrupt support.
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- tools/litex_client: Add --length parameter for MMAP read accesses.
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- software/bios/cpu: Add CPU tests in CI.
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- litex_sim/xgmii_ethernet: Improve models.
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- litex_setup: Cleanup/Simplify and switch to proper "--" commands (with retro-compat).
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- cores/jtag: Add ECP5 support.
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- cores/led: Add WS2812/NeoPixel core.
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- cpu/femtorv: Finish integration and add variants support.
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- cpu/eos-s3: Add initial support.
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- build/anlogic: Add initial support.
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- cpu/microwatt: Add Xilinx multiplier support.
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- cpu/vexriscv/cfu: Improve integration.
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- soc/interconnect: Add initial AHB support (AHB2Wishbone).
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- cpu/gowin_emcu: Add initial Gowin EMCU support.
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- cpu/zynq7000: Add initial BIOS/software support.
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- cpu/zynq7000: Add TCL support.
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- core/prbs: Add error behaviour configuration on saturation.
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- software/bios: Add write size option to mem_write cmd.
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- LitePCIe/phy: Cleanup 7-Series PHY integration.
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- LitePCIe/dma Add LitePCIeDMAStatus module.
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- LitePCIe/software: Improve kernel/user-space utilities.
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- LiteDRAM/litedram_gen: Improve ECP5 support.
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- LiteDRAM/phy: Add initial LPDDR5 support.
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- LiteDRAM/frontend: Refactor DRAM FIFO and add optional bypass mode.
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- LiteEth/core: Add 32-bit/64-bit datapath support.
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- LiteEth/phy: Add 10Gbps / Xilinx XGMII support.
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- LiteEth/phy: Add 1Gbps / Efinix RGMII support.
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- LiteSPI/phy: Simplify SDR/DDR PHYs.
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- LiteHyperBus: Add 16-bit support.
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[> API changes/Deprecation
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--------------------------
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- software: Replace libbase with picolibc (new requirements: meson/ninja).
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- amaranth: Switch from nMigen to Amaranth HDL.
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[> 2021.08, released on September 15th 2021
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-------------------------------------------
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[> Issues resolved
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------------------
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- wishbone/UpConverter: Fix SEL propagation.
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- cores/i2s: Fix SYNC sampling.
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- BIOS/lib*: Fix GCC warnings.
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- cpu/software: Fix stack alignment issues.
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- cpu/blackparrot: Fix integration.
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- interconnect/axi: Fix valid signal in connect_to_pads for axi lite.
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- software/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
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- software/soc.h: Fix interoperability with assembly.
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- interconnect/stream: Fix n=1 case on Multiplexer/Demultiplexer.
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- interconnect/axi: Fix BURST_WRAP case on AXIBurst2Beat.
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- cpu/VexRiscv-SMP: Fix build without a memory bus.
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- cpu/software: Fix CLANG detection.
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- build/software: Force a fresh software build when cpu-type/variant is changed.
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- cores/uart: Fix TX reset level.
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- BIOS: Fix PHDR link error.
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- BIOS: Fix build-id link error.
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- LiteDRAM: Fix Artix7/DDR3 calibraiton at low speed.
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[> Added Features
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-----------------
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- cores/video: Add 7-Series HDMI PHY over GTPs.
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- cores/jtagbone: Allow JTAG chain selection.
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- programmer: Add iCESugar programmer.
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- cpu/vexriscv: Add CFU support.
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- soc/controller: Add separate SoC/CPU reset fields.
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- BIOS/liblitedram: Add debug capabilities, minor improvements.
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- cpu/femtoRV: Add initial FemtoRV support.
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- cores/uart: Cleaned-up, Add optional TX-Flush.
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- cores/usb_ohci: Add initial SpinalHDL's USB OHCI support (integrated in Linux-on-LiteX-Vexriscv).
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- stream: Add Gate Module.
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- soc/builder: Allow linking external software packages.
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- soc/software: Allow registering init functions.
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- cores/ram: Add init support to Nexus LRAM.
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- cores/spi: Add Manual CS Mode for bulk transfers.
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- cores/VexRiscv-SMP: Make [ID]TLB size configurable.
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- dts: Add GPIO IRQ support.
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- programmer/DFUProg: Allow to specify alt interace and to not reboot.
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- cores/clock/ecp5: Add dynamic phase adjustment signals.
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- tools/litex_sim: Mode SDRAM settings to LiteDRAM's DFI model.
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- build/gowin: Add AsyncResetSynchronizer/DDRInput/DDROutput implementations.
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- build/gowin: Add On-Chip-Oscillator support.
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- build/gowin: Add initial timing constraints support.
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- build/attr_translate: Simplify/Cleanup.
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- programmer/OpenFPGALoader: Add cable and freq options.
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- interconnect/packet: Improve PacketFIFO to handle payload/param separately.
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- clock/ecp5: Add 4-output support.
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- LiteSPI: Simplified/Cleaned-up, new MMAP architecture, applied to LiteX-Boards.
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- soc: Add LiteSPI integration code.
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- LitePCIe: DMA/Controller Simplified/Cleaned-up.
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- soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case.
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- programmer: Add ECPprogProgrammer.
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- soc/software: Add Random access option to memtest.
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- tools: Add Renode generator script.
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- tools: Add Zephyr DTS generator script.
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- build/io: Add DDRTristate.
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- cpu/VexRiscv: Restructure config flags for dcache/icache presence.
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- litex_sim: Improve RAM/SDRAM integration and make it closer to LiteX-Boards targets.
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- build/sim: Add ODDR/IDDR/DDRSTristate simulation models.
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- litex_sim: Add SPIFlash support.
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- LiteSPI: Add DDR support and integration in LiteX (rate=1:1, 1:2).
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- build/Vivado: Make pre_synthesis/placement/routing commands similar to platform_commands.
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- LiteDRAM: Refactor C code generator.
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- LiteDRAM: Improve LPDDR4 support.
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- LiteDRAM: Reduce ECC granularity.
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[> API changes/Deprecation
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--------------------------
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- soc_core: --integrated-rom-file argument renamed to --integrated-rom-init.
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[> 2021.04, released on May 3th 2021
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------------------------------------
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[> Issues resolved
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------------------
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- litex_term: Fix Windows/OS-X support.
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- soc/USB-ACM: Fix reset clock domain.
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- litex_json2dts: Various fixes/improvements.
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- cores/clock: Fix US(P)IDELAYCTRL reset sequence.
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- cpu/Vexriscv: Fix Lite variant ABI (has multiplier so can use rv32im).
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- BIOS: Fix various compiler warnings.
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- LiteSDCard: Fix various issues, enable multiblock reads/writes and improve performance.
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- CSR: Fix address wrapping within a CSRBank.
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- soc/add_etherbone: Fix UDPIPCore clock domain.
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- stream/Gearbox: Fix some un-supported cases.
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- cpu/VexRiscv-SMP: Fix build on Intel/Altera devices with specific RAM implementation.
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- timer: Fix AutoDoc.
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- Microwatt/Ethernet: Fix build.
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- soc/software: Link with compiler instead of ld.
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[> Added Features
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-----------------
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- Lattice-NX: Allow up to 320KB RAMs.
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- BIOS: Allow compilation with UART disabled.
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- litex_json2dts: Simplify/Improve and allow VexRiscv/Mor1kx support.
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- BIOS/i2c: Improve cmd_i2c.
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- BIOS/liblitedram: Various improvements for DDR4/LPDDR.
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- cores/Timer: Add initial unit test.
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- cores: Add initial JTAGBone support on Xilinx FPGAs.
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- litex_term: Improve JTAG-UART support.
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- litex_server: Add JTAGBone support.
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- VexRiscv-SMP: Add --without-out-of-order and --with-wishbone-memory capabilities.
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- BIOS: Allow specify TRIPLE with LITEX_ENV_CC_TRIPLE.
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- litex_client: Add simple --read/--write support.
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- OpenFPGALoader: Add flash method.
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- litex_sim: Add GTKWave savefile generator.
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- litex_term: Add nios2-terminal support.
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- cpu/mor1kx: Add initial SMP support.
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- interconnect/axi: Add tkeep support.
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- cores/gpio: Add IRQ support to GPIOIn.
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- cpu: Add initial lowRISC's Ibex support.
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- build/xilinx/Vivado: Allow tcl script to be added as ip.
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- cores/uart: Rewrite PHYs to reduce resource usage and improve readability.
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- cores/pwm: Add configurable default enable/width/period values.
|
||
- cores/leds: Add optional dimming (through PWM).
|
||
- soc/add_pcie: Allow disabling MSI when not required.
|
||
- export/svd: Add constants to SVD export.
|
||
- BIOS: Allow dynamic Ethernet IP address.
|
||
- BIOS: Add boot command to boot from memory.
|
||
- cores: Add simple VideoOut core with Terminal, ColorBards, Framebuffer + various PHYs (VGA, DVI, HDMI, etc...).
|
||
- csr/EventSourceProcess: Add rising edge support and edge selection.
|
||
- soc/integration: Cleanup/Simplify soc_core/builder.
|
||
- soc/integrated_rom: Add automatic BIOS ROM resize to minimize blockram usage and improve flexibility.
|
||
- interconnect/axi: Add AXILite Clock Domain Crossing.
|
||
- cores/xadc: Add Ultrascale support.
|
||
- soc/add_ethernet: Allow nrxslots/ntxslots configuration.
|
||
- cpu/VexRiscv-SMP: Integrate FPU/RVC support.
|
||
- soc/add_csr: Add auto-allocation mode and switch to it in LiteX's code base.
|
||
- soc/BIOS: Add method to check BIOS requirements during the build and improve error message when not satisfied.
|
||
- LiteEth: Add initial timestamping support.
|
||
- litex_client: Add optional filter to --regs.
|
||
- LiteDRAM: Add LPDDR4 support.
|
||
- BIOS/netboot: Allow specifying .json file.
|
||
- cores/clock: Add initial Gowin GW1N PLL support.
|
||
- LiteSDCard: Add IRQ support.
|
||
|
||
[> API changes/Deprecation
|
||
--------------------------
|
||
- platforms/targets: Move all platforms/targets to https://github.com/litex-hub/litex-boards.
|
||
- litex_term: Remove flashing capability.
|
||
- cores/uart: Disable dynamic baudrate by default (Unused and save resources).
|
||
|
||
[> 2020.12, released on December 30th 2020
|
||
------------------------------------------
|
||
|
||
[> Issues resolved
|
||
------------------
|
||
- fix SDCard writes.
|
||
- fix crt0 .data initialize on SERV/Minerva.
|
||
- fix Zynq7000 AXI HP Slave integration.
|
||
|
||
[> Added Features
|
||
------------------
|
||
- Wishbone2CSR: Add registered version and use it on system with SDRAM.
|
||
- litex_json2dts: Add Mor1kx DTS generation support.
|
||
- Build: Add initial Radiant support for NX FPGA family.
|
||
- SoC: Allow ROM to be optionally writable (for contents overwrite over UARTBone/Etherbone).
|
||
- LiteSDCard: Improve BIOS support.
|
||
- UARTBone: Add clock domain support.
|
||
- Clocking: Uniformize reset on iCE40PLL/ECP5PLL.
|
||
- LiteDRAM: Improve calibration and add BIOS debug commands.
|
||
- Clocking: Add initial Ultrascale+ support.
|
||
- Sim: Allow dynamic enable/disable of tracing.
|
||
- BIOS: Improve memtest and report.
|
||
- BIOS: Rename/reorganize commands.
|
||
- litex_server: Simplify usage with PCIe and add debug parameter.
|
||
- LitePCIe: Add Ultrascale(+) support up to Gen3 X16.
|
||
- LiteSATA: Add BIOS/Boot integration.
|
||
- Add litex_cli to provides common RemoteClient functions: get identifier, dump regs, etc...
|
||
- LiteDRAM: Simplify BIST integration.
|
||
- Toolchains/Programmers: Improve checks/error reporting.
|
||
- BIOS: add leds command.
|
||
- SoC: Do a full reset of the SoC on reboot (not only the CPU).
|
||
- Etherbone: Improve efficiency/performance.
|
||
- LiteDRAM: Improve DDR4/DDR3 calibration.
|
||
- Build: Add initial Oxide support for NX FPGA family.
|
||
- Clock/RAM: Reorganize for better modularity.
|
||
- SPI-OPI: Various improvements for Betrusted.
|
||
- litex_json2dts: Improvements to use it with mor1kx and VexRiscv-SMP.
|
||
- Microwatt: Add IRQ support.
|
||
- BIOS: Add i2c_scan command.
|
||
- Builder: Simplify Documentation generation with --doc args on targets.
|
||
- CSR: Add documentation to EventManager registers.
|
||
- BIOS: Allow disabling timestamp for reproducible builds.
|
||
- Symbiflow: Remove workarounds on targets.
|
||
- litex_server: Simplify use on PCIe, allow direct CommXY use in scripts to bypass litex_server.
|
||
- Zynq7000: Improve PS7 configuration support (now supporting .xci/preset/dict)
|
||
- CV32E40P: Improve OBI efficiency.
|
||
- litex_term: Improve upload speed with CRC check enabled, deprecate --no-crc (no longer useful).
|
||
- BIOS: Add mem_list command to list available memory and use mem_xy commands on them.
|
||
- litex_term: Add Crossover and JTAG_UART support.
|
||
- Software: Add minimal bare metal demo app.
|
||
- UART: Add Crossover+Bridge support.
|
||
- VexRiscv-SMP: Integrate AES support.
|
||
- LitePCIe: Allow AXI mastering from FPGA (AXI-Lite and Full).
|
||
- mor1kx: Add standard+fpu and linux+fpu variants.
|
||
|
||
[> API changes/Deprecation
|
||
--------------------------
|
||
- BIOS: commands have been renamed/reorganized.
|
||
- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
|
||
- CSR: change default csr_data_width from 8 to 32.
|
||
|
||
[> 2020.08, released on August 7th 2020
|
||
---------------------------------------
|
||
|
||
[> Issues resolved
|
||
------------------
|
||
- Fix flush_cpu_icache on VexRiscv.
|
||
- Fix `.data` section placed in rom (#566)
|
||
|
||
[> Added Features
|
||
------------------
|
||
- Properly integrate Minerva CPU.
|
||
- Add nMigen dependency.
|
||
- Pluggable CPUs.
|
||
- BIOS history, autocomplete.
|
||
- Improve boards's programmers.
|
||
- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
|
||
- Speedup Memtest using an LFSR.
|
||
- Add LedChaser on boards.
|
||
- Improve WishboneBridge.
|
||
- Improve Diamond constraints.
|
||
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
|
||
- Add CV32E40P CPU support (ex RI5CY).
|
||
- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
|
||
- Add Symbiflow experimental support on Arty.
|
||
- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
|
||
- Simplify boot with boot.json configuration file.
|
||
- Revert to a single crt0 (avoid ctr/xip variants).
|
||
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
|
||
- Add AXI-Lite bus standard support.
|
||
- Add VexRiscv SMP CPU support.
|
||
|
||
[> API changes/Deprecation
|
||
--------------------------
|
||
- Add --build --load arguments to targets.
|
||
- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
|
||
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
|
||
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
|
||
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
|
||
- Rename --gateware-toolchain target parameter to --toolchain.
|
||
- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
|
||
|
||
[> 2020.04, released on April 28th, 2020
|
||
----------------------------------------
|
||
|
||
[> Description
|
||
--------------
|
||
First release of LiteX and the ecosystem of cores!
|
||
|
||
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
|
||
Cores/SoCs (with or without CPU).
|
||
|
||
The common components of a SoC are provided directly:
|
||
- Buses and Streams (Wishbone, AXI, Avalon-ST)
|
||
- Interconnect
|
||
- Common cores (RAM, ROM, Timer, UART, etc...)
|
||
- CPU wrappers/integration
|
||
- etc...
|
||
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
|
||
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
|
||
|
||
It also provides build backends for open-source and vendors toolchains.
|
||
|
||
[> Issues resolved
|
||
------------------
|
||
- NA
|
||
|
||
[> Added Features
|
||
------------------
|
||
- NA
|
||
|
||
[> API changes/Deprecation
|
||
--------------------------
|
||
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
|