128 lines
3.2 KiB
Python
128 lines
3.2 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.sim.ipc import *
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class TopLevel:
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def __init__(self, vcd_name=None, vcd_level=1,
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top_name="top", dut_type="dut", dut_name="dut",
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clk_name="sys_clk", clk_period=10, rst_name="sys_rst"):
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self.vcd_name = vcd_name
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self.vcd_level = vcd_level
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self.top_name = top_name
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self.dut_type = dut_type
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self.dut_name = dut_name
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self.clk_name = clk_name
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self.clk_period = clk_period
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self.rst_name = rst_name
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def get(self, sockaddr):
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template1 = """`timescale 1ns / 1ps
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module {top_name}();
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reg {clk_name};
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reg {rst_name};
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initial begin
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{rst_name} <= 1'b1;
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@(posedge {clk_name});
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{rst_name} <= 1'b0;
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end
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always begin
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{clk_name} <= 1'b0;
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#{hclk_period};
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{clk_name} <= 1'b1;
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#{hclk_period};
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end
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{dut_type} {dut_name}(
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.{rst_name}({rst_name}),
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.{clk_name}({clk_name})
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);
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initial $migensim_connect("{sockaddr}");
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always @(posedge {clk_name}) $migensim_tick;
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"""
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template2 = """
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initial begin
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$dumpfile("{vcd_name}");
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$dumpvars({vcd_level}, {dut_name});
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end
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"""
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r = template1.format(top_name=self.top_name,
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dut_type=self.dut_type,
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dut_name=self.dut_name,
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clk_name=self.clk_name,
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hclk_period=str(self.clk_period/2),
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rst_name=self.rst_name,
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sockaddr=sockaddr)
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if self.vcd_name is not None:
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r += template2.format(vcd_name=self.vcd_name,
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vcd_level=str(self.vcd_level),
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dut_name=self.dut_name)
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r += "\nendmodule"
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return r
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class Simulator:
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def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"):
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self.fragment = fragment
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if top_level is None:
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self.top_level = TopLevel()
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else:
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self.top_level = top_level
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self.ipc = Initiator(sockaddr)
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c_top = self.top_level.get(sockaddr)
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clk_signal = Signal(name_override=self.top_level.clk_name)
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rst_signal = Signal(name_override=self.top_level.rst_name)
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c_fragment, self.namespace = verilog.convert(fragment,
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{clk_signal, rst_signal},
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name=self.top_level.dut_type,
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clk_signal=clk_signal,
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rst_signal=rst_signal,
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return_ns=True)
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self.cycle_counter = 0
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self.interrupt = False
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self.sim_runner = sim_runner
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self.sim_runner.start(c_top, c_fragment)
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self.ipc.accept()
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reply = self.ipc.recv()
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assert(isinstance(reply, MessageTick))
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self.fragment.call_sim(self, -1)
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def run(self, ncycles=-1):
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counter = 0
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while not self.interrupt and (ncycles < 0 or counter < ncycles):
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self.ipc.send(MessageGo())
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reply = self.ipc.recv()
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assert(isinstance(reply, MessageTick))
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self.fragment.call_sim(self, self.cycle_counter)
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self.cycle_counter += 1
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counter += 1
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def rd(self, signal):
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name = self.top_level.top_name + "." \
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+ self.top_level.dut_name + "." \
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+ self.namespace.get_name(signal)
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self.ipc.send(MessageRead(name))
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reply = self.ipc.recv()
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assert(isinstance(reply, MessageReadReply))
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nbits = signal.bv.width
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value = reply.value & (2**nbits - 1)
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if signal.bv.signed and (value & 2**(nbits - 1)):
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value -= 2**nbits
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return value
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def wr(self, signal, value):
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name = self.top_level.top_name + "." \
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+ self.top_level.dut_name + "." \
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+ self.namespace.get_name(signal)
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if value < 0:
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value += 2**signal.bv.width
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assert(value >= 0 and value < 2**signal.bv.width)
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self.ipc.send(MessageWrite(name, value))
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