113 lines
2.9 KiB
Python
113 lines
2.9 KiB
Python
# Simple Processor Interface
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.bank.description import *
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from migen.flow.actor import *
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# layout is a list of tuples, either:
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# - (name, nbits, [reset value], [alignment bits])
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# - (name, sublayout)
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def _convert_layout(layout):
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r = []
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for element in layout:
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if isinstance(element[1], list):
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r.append((element[0], _convert_layout(element[1])))
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else:
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r.append((element[0], element[1]))
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return r
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def _create_csrs_assign(layout, target, atomic, prefix=""):
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csrs = []
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assigns = []
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for element in layout:
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if isinstance(element[1], list):
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r_csrs, r_assigns = _create_csrs_assign(element[1],
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atomic,
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getattr(target, element[0]),
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element[0] + "_")
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csrs += r_csrs
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assigns += r_assigns
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else:
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name = element[0]
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nbits = element[1]
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if len(element) > 2:
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reset = element[2]
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else:
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reset = 0
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if len(element) > 3:
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alignment = element[3]
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else:
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alignment = 0
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reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic, name=prefix + name)
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csrs.append(reg)
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assigns.append(getattr(target, name).eq(reg.storage[alignment:]))
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return csrs, assigns
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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class SingleGenerator(Module):
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def __init__(self, layout, mode):
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self.source = Source(_convert_layout(layout))
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self.busy = Signal()
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self._csrs, assigns = _create_csrs_assign(layout, self.source.payload,
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mode != MODE_SINGLE_SHOT)
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if mode == MODE_EXTERNAL:
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trigger = self.trigger = Signal()
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elif mode == MODE_SINGLE_SHOT:
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shoot = CSR()
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self._csrs.insert(0, shoot)
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trigger = shoot.re
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elif mode == MODE_CONTINUOUS:
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enable = CSRStorage()
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self._csrs.insert(0, enable)
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trigger = enable.storage
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else:
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raise ValueError
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self.comb += self.busy.eq(self.source.stb)
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stmts = [self.source.stb.eq(trigger)] + assigns
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self.sync += [If(self.source.ack | ~self.source.stb, *stmts)]
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def get_csrs(self):
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return self._csrs
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class Collector(Module, AutoCSR):
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def __init__(self, layout, depth=1024):
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self.sink = Sink(layout)
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self.busy = Signal()
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dw = sum(len(s) for s in self.sink.payload.flatten())
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self._r_wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
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self._r_wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
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self._r_ra = CSRStorage(bits_for(depth-1))
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self._r_rd = CSRStatus(dw)
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###
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mem = Memory(dw, depth)
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self.specials += mem
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wp = mem.get_port(write_capable=True)
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rp = mem.get_port()
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self.comb += [
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self.busy.eq(0),
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If(self._r_wc.r != 0,
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self._r_wa.we.eq(1),
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self._r_wc.we.eq(1),
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wp.we.eq(1)
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)
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),
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self._r_wa.dat_w.eq(self._r_wa.storage + 1),
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self._r_wc.dat_w.eq(self._r_wc.storage - 1),
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wp.adr.eq(self._r_wa.storage),
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wp.dat_w.eq(self.sink.payload.raw_bits()),
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rp.adr.eq(self._r_ra.storage),
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self._r_rd.status.eq(rp.dat_r)
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]
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