litex/litex
2016-03-21 20:07:03 +01:00
..
boards boards/targets: change mode (add +x) 2016-01-01 18:37:20 +01:00
build gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator 2016-03-21 19:15:40 +01:00
gen gen: remove vpi (no longer used) 2016-03-21 20:07:03 +01:00
soc soc/interconnect/stream_sim: adapt to new simulator 2016-03-21 19:56:43 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00