Florent Kermarrec dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus. ... The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX which avoid an additional dependency.		2022-03-01 09:11:55 +01:00
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__init__.py	…
test_axi.py	…
test_axi_lite.py	…
test_bitbang.py	…
test_clock.py	cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.	2022-01-25 11:09:15 +01:00
test_code_8b10b.py	…
test_cpu.py	…
test_csr.py	…
test_ecc.py	…
test_emif.py	…
test_gearbox.py	inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.	2021-03-18 13:47:10 +01:00
test_hyperbus.py	soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.	2022-03-01 09:11:55 +01:00
test_i2s.py	…
test_icap.py	…
test_packet.py	…
test_prbs.py	…
test_spi.py	…
test_spi_opi.py	…
test_stream.py	…
test_timer.py	…
test_wishbone.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00