107 lines
2.6 KiB
Python
107 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.common import *
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from lib.sata.link.scrambler import Scrambler
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Counter(Module):
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def __init__(self, width, signal=None, reset=0):
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if signal is None:
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self.value = Signal(width, reset=reset)
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else:
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self.value = signal
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self.sync += self.value.eq(self.value+1)
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class SATABIST(Module):
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def __init__(self, sector_size=512, max_count=1):
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self.sink = sink = Sink(command_rx_description(32))
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self.source = source = Source(command_tx_description(32))
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self.start = Signal()
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self.sector = Signal(48)
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self.done = Signal()
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self.ctrl_errors = Signal(32)
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self.data_errors = Signal(32)
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counter = Counter(32)
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ctrl_error_counter = Counter(32, self.ctrl_errors)
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data_error_counter = Counter(32, self.data_errors)
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self.submodules += counter, data_error_counter, ctrl_error_counter
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scrambler = InsertReset(Scrambler())
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self.submodules += scrambler
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self.comb += [
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scrambler.reset.eq(counter.reset),
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scrambler.ce.eq(counter.ce)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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ctrl_error_counter.reset.eq(1),
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data_error_counter.reset.eq(1),
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If(self.start,
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq((counter.value == 0)),
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source.eop.eq((counter.value == (sector_size*max_count)//4-1)),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(max_count),
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source.data.eq(scrambler.value),
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counter.ce.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("WAIT_WRITE_ACK")
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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sink.ack.eq(1),
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If(sink.stb,
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If(~sink.write | ~sink.success | sink.failed,
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ctrl_error_counter.ce.eq(1)
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),
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NextState("SEND_READ_CMD")
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)
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)
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fsm.act("SEND_READ_CMD",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(max_count),
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If(source.ack,
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NextState("WAIT_READ_ACK")
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)
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)
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fsm.act("WAIT_READ_ACK",
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counter.reset.eq(1),
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If(sink.stb & sink.read,
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If(~sink.read | ~sink.success | sink.failed,
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ctrl_error_counter.ce.eq(1)
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),
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NextState("RECEIVE_READ_DATA")
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)
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)
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fsm.act("RECEIVE_READ_DATA",
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sink.ack.eq(1),
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != scrambler.value,
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data_error_counter.ce.eq(1)
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),
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If(sink.eop,
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NextState("IDLE")
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)
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)
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)
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