84 lines
2.0 KiB
Python
84 lines
2.0 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from misoclib.com.spi import SPIMaster
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class SPISlave(Module):
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def __init__(self, pads, width):
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self.pads = pads
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self.width = width
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###
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self.mosi = 0
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self.miso = 0
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self.last_cs_n = 1
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self.last_clk = 0
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def get_mosi(self):
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return self.mosi
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def set_miso(self, value):
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self.miso = value
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def do_simulation(self, selfp):
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# detect edges
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cs_n_rising = 0
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cs_n_falling = 0
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clk_rising = 0
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clk_falling = 0
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if selfp.pads.cs_n and not self.last_cs_n:
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cs_n_rising = 1
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if not selfp.pads.cs_n and self.last_cs_n:
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cs_n_falling = 1
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if selfp.pads.clk and not self.last_clk:
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clk_rising = 1
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if not selfp.pads.clk and self.last_clk:
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clk_falling = 1
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# input mosi
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if clk_falling and not selfp.pads.cs_n:
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self.mosi = self.mosi << 1
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self.mosi |= selfp.pads.mosi
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# output miso
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if (clk_rising and not selfp.pads.cs_n):
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selfp.pads.miso = (self.miso >> (self.width-1)) & 0x1
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self.miso = self.miso << 1
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# save signal states
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self.last_cs_n = selfp.pads.cs_n
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self.last_clk = selfp.pads.clk
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def spi_access(selfp, length, mosi):
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selfp.spi_master._mosi.storage = mosi
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yield
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selfp.spi_master._ctrl.r = (length << 8) | 1
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selfp.spi_master._ctrl.re = 1
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yield
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selfp.spi_master._ctrl.r = 0
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selfp.spi_master._ctrl.re = 0
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yield
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while not (selfp.spi_master._status.status & 0x1):
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yield
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class TB(Module):
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def __init__(self):
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pads = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)])
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self.submodules.spi_master = SPIMaster(pads, 24, 4)
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self.submodules.spi_slave = SPISlave(pads, 24)
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def gen_simulation(self, selfp):
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for i in range(16):
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yield
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self.spi_slave.set_miso(0x123457)
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yield from spi_access(selfp, 8, 0x123457)
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print("{:08x}".format(self.spi_slave.get_mosi()))
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print("{:08x}".format(selfp.spi_master._miso.status))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True) |