87 lines
3.4 KiB
Python
87 lines
3.4 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone, csr
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from migen.genlib.record import *
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from misoclib.mem.sdram.core import SDRAMCore
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from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
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from misoclib.soc import SoC, mem_decoder
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class SDRAMSoC(SoC):
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csr_map = {
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"sdram": 8,
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"wishbone2lasmi": 9,
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"memtest_w": 10,
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"memtest_r": 11
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform, clk_freq,
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ramcon_type="lasmicon",
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with_l2=True, l2_size=8192,
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with_bandwidth=False, # specific to LASMICON,
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with_memtest=False, # ignored for MINICON
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**kwargs):
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SoC.__init__(self, platform, clk_freq, **kwargs)
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self.ramcon_type = ramcon_type
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self.with_l2 = with_l2
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self.l2_size = l2_size
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self.with_memtest = with_memtest
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self.with_bandwidth = with_bandwidth or with_memtest
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self._sdram_phy_registered = False
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def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings):
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if self._sdram_phy_registered:
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raise FinalizeError
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self._sdram_phy_registered = True
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if self.ramcon_type == "minicon" and phy.settings.memtype != "SDR":
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raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
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# Core
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self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings)
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# LASMICON frontend
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if self.ramcon_type == "lasmicon":
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if self.with_bandwidth:
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self.sdram.controller.multiplexer.add_bandwidth()
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
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if self.with_l2:
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# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
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# Remove this workaround when fixed by Xilinx.
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
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else:
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
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lasmic = self.sdram.controller.lasmic
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main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
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self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size)
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# MINICON frontend
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elif self.ramcon_type == "minicon":
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sdram_width = flen(self.sdram.controller.bus.dat_r)
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main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
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if sdram_width == 32:
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self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)
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elif sdram_width < 32:
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self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
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self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
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self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size)
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else:
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raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
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def do_finalize(self):
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if not self.with_main_ram:
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if not self._sdram_phy_registered:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
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SoC.do_finalize(self)
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