30 lines
1.0 KiB
Python
30 lines
1.0 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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class ASMIprobe(Module):
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def __init__(self, hub, trace_depth=16):
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slots = hub.get_slots()
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slot_count = len(slots)
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self._slot_count = CSRStatus(bits_for(slot_count))
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self._trace_depth = CSRStatus(bits_for(trace_depth))
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self._slot_status = [CSRStatus(2, name="slot_status" + str(i)) for i in range(slot_count)]
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self._trace = [CSRStatus(bits_for(slot_count-1), name="trace" + str(i)) for i in range(trace_depth)]
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###
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self.comb += [
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self._slot_count.status.eq(slot_count),
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self._trace_depth.status.eq(trace_depth)
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]
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for slot, status in zip(slots, self._slot_status):
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self.sync += status.status.eq(slot.state)
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shift_tags = [self._trace[n].status.eq(self._trace[n+1].status)
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for n in range(len(self._trace) - 1)]
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shift_tags.append(self._trace[-1].status.eq(hub.tag_call))
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self.sync += If(hub.call, *shift_tags)
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def get_csrs(self):
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return [self._slot_count, self._trace_depth] + self._slot_status + self._trace
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