243 lines
6.7 KiB
Python
243 lines
6.7 KiB
Python
from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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_arp_table_layout = [
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("reply", 1),
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("request", 1),
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("ip_address", 32),
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("mac_address", 48)
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]
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class LiteEthARPDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_arp_description(8),
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arp_header,
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arp_header_len)
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class LiteEthARPPacketizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_arp_description(8),
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eth_mac_description(8),
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arp_header,
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arp_header_len)
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class LiteEthARPTX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = Sink(_arp_table_layout)
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self.source = Source(eth_mac_description(8))
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###
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packetizer = LiteEthARPPacketizer()
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self.submodules += packetizer
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source = packetizer.sink
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counter = Counter(max=arp_packet_length)
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self.submodules += counter
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb,
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sink.ack.eq(0),
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NextState("SEND")
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)
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)
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self.comb += [
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source.hardware_type.eq(arp_hwtype_ethernet),
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source.protocol_type.eq(arp_proto_ip),
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source.hardware_address_length.eq(6),
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source.protocol_address_length.eq(4),
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source.source_mac_address.eq(mac_address),
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source.source_ip_address.eq(ip_address),
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If(sink.reply,
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source.operation.eq(arp_opcode_reply),
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source.destination_mac_address.eq(sink.mac_address),
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source.destination_ip_address.eq(sink.ip_address)
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).Elif(sink.request,
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source.operation.eq(arp_opcode_request),
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source.destination_mac_address.eq(0xffffffffffff),
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source.destination_ip_address.eq(sink.ip_address)
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)
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]
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fsm.act("SEND",
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source.stb.eq(1),
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == arp_packet_length-1),
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Record.connect(packetizer.source, self.source),
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self.source.destination_mac_address.eq(source.destination_mac_address),
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self.source.source_mac_address.eq(mac_address),
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self.source.ethernet_type.eq(ethernet_type_arp),
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If(self.source.stb & self.source.ack,
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sink.ack.eq(source.eop),
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counter.ce.eq(1),
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If(self.source.eop,
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NextState("IDLE")
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)
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)
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)
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class LiteEthARPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = Sink(eth_mac_description(8))
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self.source = source = Source(_arp_table_layout)
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###
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depacketizer = LiteEthARPDepacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(
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sink.stb &
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(sink.hardware_type == arp_hwtype_ethernet) &
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(sink.protocol_type == arp_proto_ip) &
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(sink.hardware_address_length == 6) &
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(sink.protocol_address_length == 4) &
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(sink.destination_ip_address == ip_address)
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)
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reply = Signal()
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request = Signal()
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self.comb += Case(sink.operation, {
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arp_opcode_request : [request.eq(1)],
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arp_opcode_reply : [reply.eq(1)],
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"default" : []
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})
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self.comb += [
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source.ip_address.eq(sink.source_ip_address),
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source.mac_address.eq(sink.source_mac_address)
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]
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fsm.act("CHECK",
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If(valid,
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source.stb.eq(1),
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source.reply.eq(reply),
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source.request.eq(request)
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),
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NextState("TERMINATE")
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),
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fsm.act("TERMINATE",
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sink.ack.eq(1),
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If(sink.stb & sink.eop,
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NextState("IDLE")
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)
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)
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class LiteEthARPTable(Module):
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def __init__(self):
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self.sink = sink = Sink(_arp_table_layout) # from arp_rx
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self.source = source = Source(_arp_table_layout) # to arp_tx
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# Request/Response interface
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self.request = request = Sink(arp_table_request_layout)
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self.response = response = Source(arp_table_response_layout)
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###
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request_timeout = Timeout(512) # XXX fix me 100ms?
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request_pending = FlipFlop()
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request_ip_address = FlipFlop(32, reset=0xffffffff) # XXX add cached_valid?
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self.submodules += request_timeout, request_pending, request_ip_address
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self.comb += [
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request_timeout.ce.eq(request_pending.q),
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request_pending.d.eq(1),
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request_ip_address.d.eq(request.ip_address)
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]
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# Note: Store only one ip/mac couple, replace this with
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# a real ARP table
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update = Signal()
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cached_ip_address = Signal(32)
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cached_mac_address = Signal(48)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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# Note: for simplicicy, if APR table is busy response from arp_rx
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# is lost. This is compensated by the protocol (retrys)
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If(sink.stb & sink.request,
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NextState("SEND_REPLY")
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).Elif(sink.stb & sink.reply & request_pending.q,
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NextState("UPDATE_TABLE"),
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).Elif(request.stb | (request_pending.q & request_timeout.reached),
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NextState("CHECK_TABLE")
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)
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)
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fsm.act("SEND_REPLY",
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source.stb.eq(1),
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source.reply.eq(1),
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source.ip_address.eq(sink.ip_address),
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If(source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("UPDATE_TABLE",
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request_pending.reset.eq(1),
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update.eq(1),
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NextState("CHECK_TABLE")
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)
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self.sync += [
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If(update,
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cached_ip_address.eq(sink.ip_address),
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cached_mac_address.eq(sink.mac_address)
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)
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]
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found = Signal()
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fsm.act("CHECK_TABLE",
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# XXX: add a live time for cached_mac_address
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If(request_ip_address.q == cached_ip_address,
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request_ip_address.reset.eq(1),
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NextState("PRESENT_RESPONSE"),
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).Elif(request.ip_address == cached_ip_address,
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request.ack.eq(request.stb),
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NextState("PRESENT_RESPONSE"),
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).Else(
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request_ip_address.ce.eq(1),
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NextState("SEND_REQUEST")
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)
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)
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fsm.act("SEND_REQUEST",
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source.stb.eq(1),
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source.request.eq(1),
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source.ip_address.eq(request.ip_address),
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If(source.ack,
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request_timeout.reset.eq(1),
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request_pending.ce.eq(1),
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request.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("PRESENT_RESPONSE",
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response.stb.eq(1),
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response.failed.eq(0), # XXX add timeout to trigger failed
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response.mac_address.eq(cached_mac_address),
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If(response.ack,
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NextState("IDLE")
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)
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)
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class LiteEthARP(Module):
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def __init__(self, mac, mac_address, ip_address):
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self.submodules.tx = LiteEthARPTX(mac_address, ip_address)
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self.submodules.rx = LiteEthARPRX(mac_address, ip_address)
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self.submodules.table = LiteEthARPTable()
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self.comb += [
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Record.connect(self.rx.source, self.table.sink),
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Record.connect(self.table.source, self.tx.sink)
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]
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mac_port = mac.crossbar.get_port(ethernet_type_arp)
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self.comb += [
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Record.connect(self.tx.source, mac_port.sink),
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Record.connect(mac_port.source, self.rx.sink)
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]
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