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e11d9b9322
litex
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migen
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bank
History
Sebastien Bourdeauducq
8a61d9d121
bus/csr: Rename a->adr d->dat to be consistent with the other buses
2012-02-13 21:46:39 +01:00
..
__init__.py
Cleanup
2011-12-05 19:25:32 +01:00
csrgen.py
bus/csr: Rename a->adr d->dat to be consistent with the other buses
2012-02-13 21:46:39 +01:00
description.py
bank: support registers larger than the bus word width
2012-02-06 16:15:27 +01:00
eventmanager.py
bank: event manager
2012-02-06 17:39:32 +01:00