108 lines
2.9 KiB
Python
108 lines
2.9 KiB
Python
import os
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from distutils.version import StrictVersion
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from migen.fhdl.std import *
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from migen.fhdl.specials import SynthesisDirective
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.io import *
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from mibuild import tools
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def settings(path, ver=None, sub=None):
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vers = list(tools.versions(path))
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if ver is None:
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ver = max(vers)
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else:
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ver = StrictVersion(ver)
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assert ver in vers
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full = os.path.join(path, str(ver))
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if sub:
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full = os.path.join(full, sub)
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search = [64, 32]
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if tools.arch_bits() == 32:
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search.reverse()
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for b in search:
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settings = os.path.join(full, "settings{0}.sh".format(b))
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if os.path.exists(settings):
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return settings
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raise OSError("no settings file found")
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class XilinxNoRetimingImpl(Module):
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def __init__(self, reg):
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self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
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class XilinxNoRetiming:
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@staticmethod
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def lower(dr):
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return XilinxNoRetimingImpl(dr.reg)
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class XilinxMultiRegImpl(MultiRegImpl):
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def __init__(self, *args, **kwargs):
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MultiRegImpl.__init__(self, *args, **kwargs)
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self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs]
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class XilinxMultiReg:
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
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class XilinxAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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self.specials += [
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Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=rst1),
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Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=cd.rst)
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]
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class XilinxAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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class XilinxDifferentialInputImpl(Module):
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def __init__(self, i_p, i_n, o):
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self.specials += Instance("IBUFDS", i_I=i_p, i_IB=i_n, o_O=o)
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class XilinxDifferentialInput:
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@staticmethod
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def lower(dr):
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return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
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class XilinxDifferentialOutputImpl(Module):
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def __init__(self, i, o_p, o_n):
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self.specials += Instance("OBUFDS", i_I=i, o_O=o_p, o_OB=o_n)
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class XilinxDifferentialOutput:
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@staticmethod
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def lower(dr):
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return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
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class XilinxDDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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self.specials += Instance("ODDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=clk, i_CE=1, i_S=0, i_R=0,
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i_D1=i1, i_D2=i2, o_Q=o,
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)
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class XilinxDDROutput:
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@staticmethod
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def lower(dr):
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return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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xilinx_special_overrides = {
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NoRetiming: XilinxNoRetiming,
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MultiReg: XilinxMultiReg,
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
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DifferentialInput: XilinxDifferentialInput,
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DifferentialOutput: XilinxDifferentialOutput,
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DDROutput: XilinxDDROutput
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}
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