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31 lines
376 B
Verilog
31 lines
376 B
Verilog
module psync(
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input clk1,
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input i,
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input clk2,
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output o
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);
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reg level;
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always @(posedge clk1)
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if(i)
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level <= ~level;
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reg level1;
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reg level2;
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reg level3;
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always @(posedge clk2) begin
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level1 <= level;
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level2 <= level1;
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level3 <= level2;
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end
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assign o = level2 ^ level3;
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initial begin
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level <= 1'b0;
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level1 <= 1'b0;
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level2 <= 1'b0;
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level3 <= 1'b0;
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end
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endmodule
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