830 lines
32 KiB
Verilog
830 lines
32 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_load_store_unit.v
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// Title : Load and store unit
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : Instead of disallowing an instruction cache miss on a data cache
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// : miss, both can now occur at the same time. If both occur at same
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// : time, then restart address is the address of instruction that
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// : caused data cache miss.
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// Version : 3.2
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// : EBRs use SYNC resets instead of ASYNC resets.
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// Version : 3.3
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// : Support for new non-cacheable Data Memory that is accessible by
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// : the data port and has a one cycle access latency.
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// Version : 3.4
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// : No change
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// Version : 3.5
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// : Bug fix: Inline memory is correctly generated if it is not a
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// : power-of-two
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_load_store_unit (
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// ----- Inputs -------
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clk_i,
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rst_i,
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// From pipeline
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stall_a,
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stall_x,
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stall_m,
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kill_x,
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kill_m,
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exception_m,
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store_operand_x,
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load_store_address_x,
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load_store_address_m,
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load_store_address_w,
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load_x,
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store_x,
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load_q_x,
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store_q_x,
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load_q_m,
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store_q_m,
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sign_extend_x,
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size_x,
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`ifdef CFG_DCACHE_ENABLED
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dflush,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_data_m,
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`endif
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// From Wishbone
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d_dat_i,
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d_ack_i,
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d_err_i,
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d_rty_i,
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// ----- Outputs -------
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// To pipeline
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`ifdef CFG_DCACHE_ENABLED
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dcache_refill_request,
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dcache_restart_request,
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dcache_stall_request,
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dcache_refilling,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_store_data_m,
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irom_address_xm,
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irom_we_xm,
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irom_stall_request_x,
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`endif
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load_data_w,
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stall_wb_load,
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// To Wishbone
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d_dat_o,
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d_adr_o,
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d_cyc_o,
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d_sel_o,
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d_stb_o,
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d_we_o,
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d_cti_o,
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d_lock_o,
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d_bte_o
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter associativity = 1; // Associativity of the cache (Number of ways)
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parameter sets = 512; // Number of sets
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parameter bytes_per_line = 16; // Number of bytes per cache line
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input stall_a; // A stage stall
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input stall_x; // X stage stall
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input stall_m; // M stage stall
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input kill_x; // Kill instruction in X stage
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input kill_m; // Kill instruction in M stage
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input exception_m; // An exception occured in the M stage
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input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
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input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
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input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
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input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
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input load_x; // Load instruction in X stage
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input store_x; // Store instruction in X stage
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input load_q_x; // Load instruction in X stage
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input store_q_x; // Store instruction in X stage
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input load_q_m; // Load instruction in M stage
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input store_q_m; // Store instruction in M stage
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input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
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input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
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`ifdef CFG_DCACHE_ENABLED
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input dflush; // Flush the data cache
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`endif
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`ifdef CFG_IROM_ENABLED
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input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
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`endif
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input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
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input d_ack_i; // Data Wishbone interface acknowledgement
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input d_err_i; // Data Wishbone interface error
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input d_rty_i; // Data Wishbone interface retry
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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`ifdef CFG_DCACHE_ENABLED
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output dcache_refill_request; // Request to refill data cache
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wire dcache_refill_request;
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output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
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wire dcache_restart_request;
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output dcache_stall_request; // Data cache stall request
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wire dcache_stall_request;
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output dcache_refilling;
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wire dcache_refilling;
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`endif
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`ifdef CFG_IROM_ENABLED
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output irom_store_data_m; // Store data to Instruction ROM
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wire [`LM32_WORD_RNG] irom_store_data_m;
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output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
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wire [`LM32_WORD_RNG] irom_address_xm;
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output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
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wire irom_we_xm;
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output irom_stall_request_x; // Stall instruction in D stage
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wire irom_stall_request_x;
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`endif
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output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
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reg [`LM32_WORD_RNG] load_data_w;
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output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
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reg stall_wb_load;
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output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
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reg [`LM32_WORD_RNG] d_dat_o;
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output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
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reg [`LM32_WORD_RNG] d_adr_o;
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output d_cyc_o; // Data Wishbone interface cycle
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reg d_cyc_o;
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output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
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reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
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output d_stb_o; // Data Wishbone interface strobe
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reg d_stb_o;
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output d_we_o; // Data Wishbone interface write enable
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reg d_we_o;
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output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
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reg [`LM32_CTYPE_RNG] d_cti_o;
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output d_lock_o; // Date Wishbone interface lock bus
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reg d_lock_o;
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output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] d_bte_o;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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// Microcode pipeline registers - See inputs for description
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reg [`LM32_SIZE_RNG] size_m;
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reg [`LM32_SIZE_RNG] size_w;
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reg sign_extend_m;
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reg sign_extend_w;
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reg [`LM32_WORD_RNG] store_data_x;
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reg [`LM32_WORD_RNG] store_data_m;
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reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
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reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
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wire [`LM32_WORD_RNG] data_m;
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reg [`LM32_WORD_RNG] data_w;
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`ifdef CFG_DCACHE_ENABLED
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wire dcache_select_x; // Select data cache to load from / store to
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reg dcache_select_m;
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wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
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wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
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reg dcache_refill_ready; // Indicates the next word of refill data is ready
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wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
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wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
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wire last_word; // Indicates if this is the last word in the cache line
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wire [`LM32_WORD_RNG] first_address; // First cache refill address
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`endif
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`ifdef CFG_DRAM_ENABLED
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wire dram_select_x; // Select data RAM to load from / store to
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reg dram_select_m;
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reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
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reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
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wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
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wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
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wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
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`endif
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wire wb_select_x; // Select Wishbone to load from / store to
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`ifdef CFG_IROM_ENABLED
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wire irom_select_x; // Select instruction ROM to load from / store to
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reg irom_select_m;
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`endif
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reg wb_select_m;
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reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
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reg wb_load_complete; // Indicates when a Wishbone load is complete
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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`ifdef CFG_DRAM_ENABLED
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// Data RAM
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pmi_ram_dp_true
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#(
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// ----- Parameters -------
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.pmi_family (`LATTICE_FAMILY),
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//.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_data_width_a (`LM32_WORD_WIDTH),
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//.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
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//.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
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.pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_data_width_a (`LM32_WORD_WIDTH),
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.pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
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.pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
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.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_regmode_a ("noreg"),
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.pmi_regmode_b ("noreg"),
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.pmi_gsr ("enable"),
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.pmi_resetmode ("sync"),
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.pmi_init_file (`CFG_DRAM_INIT_FILE),
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.pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT),
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.module_type ("pmi_ram_dp_true")
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)
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ram (
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// ----- Inputs -------
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.ClockA (clk_i),
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.ClockB (clk_i),
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.ResetA (rst_i),
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.ResetB (rst_i),
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.DataInA ({32{1'b0}}),
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.DataInB (dram_store_data_m),
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.AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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// .ClockEnA (!stall_x & (load_x | store_x)),
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.ClockEnA (!stall_x),
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.ClockEnB (!stall_m),
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.WrA (`FALSE),
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.WrB (store_q_m & dram_select_m),
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// ----- Outputs -------
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.QA (dram_data_out),
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.QB ()
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);
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/*----------------------------------------------------------------------
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EBRs cannot perform reads from location 'written to' on the same clock
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edge. Therefore bypass logic is required to latch the store'd value
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and use it for the load (instead of value from memory).
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----------------------------------------------------------------------*/
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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if (rst_i == `TRUE)
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begin
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dram_bypass_en <= `FALSE;
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dram_bypass_data <= 0;
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end
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else
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begin
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if (stall_x == `FALSE)
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dram_bypass_data <= dram_store_data_m;
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if ( (stall_m == `FALSE)
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&& (stall_x == `FALSE)
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&& (store_q_m == `TRUE)
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&& ( (load_x == `TRUE)
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|| (store_x == `TRUE)
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)
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&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
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)
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dram_bypass_en <= `TRUE;
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else
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if ( (dram_bypass_en == `TRUE)
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&& (stall_x == `FALSE)
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)
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dram_bypass_en <= `FALSE;
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end
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assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
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`endif
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`ifdef CFG_DCACHE_ENABLED
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// Data cache
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lm32_dcache #(
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.associativity (associativity),
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.sets (sets),
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.bytes_per_line (bytes_per_line),
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.base_address (base_address),
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.limit (limit)
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) dcache (
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// ----- Inputs -----
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.clk_i (clk_i),
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.rst_i (rst_i),
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.stall_a (stall_a),
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.stall_x (stall_x),
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.stall_m (stall_m),
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.address_x (load_store_address_x),
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.address_m (load_store_address_m),
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.load_q_m (load_q_m & dcache_select_m),
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.store_q_m (store_q_m & dcache_select_m),
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.store_data (store_data_m),
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.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
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.refill_ready (dcache_refill_ready),
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.refill_data (wb_data_m),
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.dflush (dflush),
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// ----- Outputs -----
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.stall_request (dcache_stall_request),
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.restart_request (dcache_restart_request),
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.refill_request (dcache_refill_request),
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.refill_address (dcache_refill_address),
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.refilling (dcache_refilling),
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.load_data (dcache_data_m)
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);
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`endif
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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// Select where data should be loaded from / stored to
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`ifdef CFG_DRAM_ENABLED
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assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
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&& (load_store_address_x <= `CFG_DRAM_LIMIT);
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`endif
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`ifdef CFG_IROM_ENABLED
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assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
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&& (load_store_address_x <= `CFG_IROM_LIMIT);
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`endif
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`ifdef CFG_DCACHE_ENABLED
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assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
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&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
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`ifdef CFG_DRAM_ENABLED
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&& (dram_select_x == `FALSE)
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`endif
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`ifdef CFG_IROM_ENABLED
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&& (irom_select_x == `FALSE)
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`endif
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;
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`endif
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assign wb_select_x = `TRUE
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`ifdef CFG_DCACHE_ENABLED
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&& !dcache_select_x
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`endif
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`ifdef CFG_DRAM_ENABLED
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&& !dram_select_x
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`endif
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`ifdef CFG_IROM_ENABLED
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&& !irom_select_x
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`endif
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;
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// Make sure data to store is in correct byte lane
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always @(*)
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begin
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case (size_x)
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`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
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`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
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`LM32_SIZE_WORD: store_data_x = store_operand_x;
|
|
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
|
|
endcase
|
|
end
|
|
|
|
// Generate byte enable accoring to size of load or store and address being accessed
|
|
always @(*)
|
|
begin
|
|
casez ({size_x, load_store_address_x[1:0]})
|
|
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
|
|
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
|
|
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
|
|
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
|
|
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
|
|
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
|
|
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
|
|
default: byte_enable_x = 4'bxxxx;
|
|
endcase
|
|
end
|
|
|
|
`ifdef CFG_DRAM_ENABLED
|
|
// Only replace selected bytes
|
|
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
|
|
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
|
|
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
|
|
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
|
|
`endif
|
|
|
|
`ifdef CFG_IROM_ENABLED
|
|
// Only replace selected bytes
|
|
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
|
|
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
|
|
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
|
|
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
|
|
`endif
|
|
|
|
`ifdef CFG_IROM_ENABLED
|
|
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
|
|
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
|
|
// byte is replaced, and the whole 32-bit value is written back
|
|
|
|
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
|
|
? load_store_address_m
|
|
: load_store_address_x;
|
|
|
|
// All store instructions perform a write operation in the M stage
|
|
assign irom_we_xm = (irom_select_m == `TRUE)
|
|
&& (store_q_m == `TRUE);
|
|
|
|
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
|
|
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
|
|
// allow load (or store) instructions sequentially after the store instructions to proceed
|
|
// until the store instruction has vacated M stage (i.e., completed the store operation)
|
|
assign irom_stall_request_x = (irom_select_x == `TRUE)
|
|
&& (store_q_x == `TRUE);
|
|
`endif
|
|
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
`ifdef CFG_DRAM_ENABLED
|
|
`ifdef CFG_IROM_ENABLED
|
|
// WB + DC + DRAM + IROM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: dram_select_m == `TRUE
|
|
? dram_data_m
|
|
: irom_select_m == `TRUE
|
|
? irom_data_m
|
|
: dcache_data_m;
|
|
`else
|
|
// WB + DC + DRAM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: dram_select_m == `TRUE
|
|
? dram_data_m
|
|
: dcache_data_m;
|
|
`endif
|
|
`else
|
|
`ifdef CFG_IROM_ENABLED
|
|
// WB + DC + IROM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: irom_select_m == `TRUE
|
|
? irom_data_m
|
|
: dcache_data_m;
|
|
`else
|
|
// WB + DC
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: dcache_data_m;
|
|
`endif
|
|
`endif
|
|
`else
|
|
`ifdef CFG_DRAM_ENABLED
|
|
`ifdef CFG_IROM_ENABLED
|
|
// WB + DRAM + IROM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: dram_select_m == `TRUE
|
|
? dram_data_m
|
|
: irom_data_m;
|
|
`else
|
|
// WB + DRAM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: dram_data_m;
|
|
`endif
|
|
`else
|
|
`ifdef CFG_IROM_ENABLED
|
|
// WB + IROM
|
|
assign data_m = wb_select_m == `TRUE
|
|
? wb_data_m
|
|
: irom_data_m;
|
|
`else
|
|
// WB
|
|
assign data_m = wb_data_m;
|
|
`endif
|
|
`endif
|
|
`endif
|
|
|
|
// Sub-word selection and sign/zero-extension for loads
|
|
always @(*)
|
|
begin
|
|
casez ({size_w, load_store_address_w[1:0]})
|
|
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
|
|
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
|
|
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
|
|
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
|
|
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
|
|
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
|
|
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
|
|
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
|
|
endcase
|
|
end
|
|
|
|
// Unused/constant Wishbone signals
|
|
assign d_bte_o = `LM32_BTYPE_LINEAR;
|
|
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
// Generate signal to indicate last word in cache line
|
|
generate
|
|
case (bytes_per_line)
|
|
4:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_END;
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
|
assign last_word = `TRUE;
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
|
|
end
|
|
8:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
|
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
|
|
end
|
|
16:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
|
assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
|
|
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
|
|
end
|
|
endcase
|
|
endgenerate
|
|
`endif
|
|
|
|
/////////////////////////////////////////////////////
|
|
// Sequential Logic
|
|
/////////////////////////////////////////////////////
|
|
|
|
// Data Wishbone interface
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
d_cyc_o <= `FALSE;
|
|
d_stb_o <= `FALSE;
|
|
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
|
|
d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
|
d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
|
|
d_we_o <= `FALSE;
|
|
d_cti_o <= `LM32_CTYPE_END;
|
|
d_lock_o <= `FALSE;
|
|
wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
|
|
wb_load_complete <= `FALSE;
|
|
stall_wb_load <= `FALSE;
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
dcache_refill_ready <= `FALSE;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
// Refill ready should only be asserted for a single cycle
|
|
dcache_refill_ready <= `FALSE;
|
|
`endif
|
|
// Is a Wishbone cycle already in progress?
|
|
if (d_cyc_o == `TRUE)
|
|
begin
|
|
// Is the cycle complete?
|
|
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
|
|
begin
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
if ((dcache_refilling == `TRUE) && (!last_word))
|
|
begin
|
|
// Fetch next word of cache line
|
|
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
|
|
end
|
|
else
|
|
`endif
|
|
begin
|
|
// Refill/access complete
|
|
d_cyc_o <= `FALSE;
|
|
d_stb_o <= `FALSE;
|
|
d_lock_o <= `FALSE;
|
|
end
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
d_cti_o <= next_cycle_type;
|
|
// If we are performing a refill, indicate to cache next word of data is ready
|
|
dcache_refill_ready <= dcache_refilling;
|
|
`endif
|
|
// Register data read from Wishbone interface
|
|
wb_data_m <= d_dat_i;
|
|
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
|
|
wb_load_complete <= !d_we_o;
|
|
end
|
|
// synthesis translate_off
|
|
if (d_err_i == `TRUE)
|
|
$display ("Data bus error. Address: %x", d_adr_o);
|
|
// synthesis translate_on
|
|
end
|
|
else
|
|
begin
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
if (dcache_refill_request == `TRUE)
|
|
begin
|
|
// Start cache refill
|
|
d_adr_o <= first_address;
|
|
d_cyc_o <= `TRUE;
|
|
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
|
|
d_stb_o <= `TRUE;
|
|
d_we_o <= `FALSE;
|
|
d_cti_o <= first_cycle_type;
|
|
//d_lock_o <= `TRUE;
|
|
end
|
|
else
|
|
`endif
|
|
if ( (store_q_m == `TRUE)
|
|
&& (stall_m == `FALSE)
|
|
`ifdef CFG_DRAM_ENABLED
|
|
&& (dram_select_m == `FALSE)
|
|
`endif
|
|
`ifdef CFG_IROM_ENABLED
|
|
&& (irom_select_m == `FALSE)
|
|
`endif
|
|
)
|
|
begin
|
|
// Data cache is write through, so all stores go to memory
|
|
d_dat_o <= store_data_m;
|
|
d_adr_o <= load_store_address_m;
|
|
d_cyc_o <= `TRUE;
|
|
d_sel_o <= byte_enable_m;
|
|
d_stb_o <= `TRUE;
|
|
d_we_o <= `TRUE;
|
|
d_cti_o <= `LM32_CTYPE_END;
|
|
end
|
|
else if ( (load_q_m == `TRUE)
|
|
&& (wb_select_m == `TRUE)
|
|
&& (wb_load_complete == `FALSE)
|
|
// stall_m will be TRUE, because stall_wb_load will be TRUE
|
|
)
|
|
begin
|
|
// Read requested address
|
|
stall_wb_load <= `FALSE;
|
|
d_adr_o <= load_store_address_m;
|
|
d_cyc_o <= `TRUE;
|
|
d_sel_o <= byte_enable_m;
|
|
d_stb_o <= `TRUE;
|
|
d_we_o <= `FALSE;
|
|
d_cti_o <= `LM32_CTYPE_END;
|
|
end
|
|
end
|
|
// Clear load/store complete flag when instruction leaves M stage
|
|
if (stall_m == `FALSE)
|
|
wb_load_complete <= `FALSE;
|
|
// When a Wishbone load first enters the M stage, we need to stall it
|
|
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
|
|
stall_wb_load <= `TRUE;
|
|
// Clear stall request if load instruction is killed
|
|
if ((kill_m == `TRUE) || (exception_m == `TRUE))
|
|
stall_wb_load <= `FALSE;
|
|
end
|
|
end
|
|
|
|
// Pipeline registers
|
|
|
|
// X/M stage pipeline registers
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
sign_extend_m <= `FALSE;
|
|
size_m <= 2'b00;
|
|
byte_enable_m <= `FALSE;
|
|
store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
dcache_select_m <= `FALSE;
|
|
`endif
|
|
`ifdef CFG_DRAM_ENABLED
|
|
dram_select_m <= `FALSE;
|
|
`endif
|
|
`ifdef CFG_IROM_ENABLED
|
|
irom_select_m <= `FALSE;
|
|
`endif
|
|
wb_select_m <= `FALSE;
|
|
end
|
|
else
|
|
begin
|
|
if (stall_m == `FALSE)
|
|
begin
|
|
sign_extend_m <= sign_extend_x;
|
|
size_m <= size_x;
|
|
byte_enable_m <= byte_enable_x;
|
|
store_data_m <= store_data_x;
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
dcache_select_m <= dcache_select_x;
|
|
`endif
|
|
`ifdef CFG_DRAM_ENABLED
|
|
dram_select_m <= dram_select_x;
|
|
`endif
|
|
`ifdef CFG_IROM_ENABLED
|
|
irom_select_m <= irom_select_x;
|
|
`endif
|
|
wb_select_m <= wb_select_x;
|
|
end
|
|
end
|
|
end
|
|
|
|
// M/W stage pipeline registers
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
size_w <= 2'b00;
|
|
data_w <= {`LM32_WORD_WIDTH{1'b0}};
|
|
sign_extend_w <= `FALSE;
|
|
end
|
|
else
|
|
begin
|
|
size_w <= size_m;
|
|
data_w <= data_m;
|
|
sign_extend_w <= sign_extend_m;
|
|
end
|
|
end
|
|
|
|
/////////////////////////////////////////////////////
|
|
// Behavioural Logic
|
|
/////////////////////////////////////////////////////
|
|
|
|
// synthesis translate_off
|
|
|
|
// Check for non-aligned loads or stores
|
|
always @(posedge clk_i)
|
|
begin
|
|
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
|
|
begin
|
|
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
|
|
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
|
|
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
|
|
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
|
|
end
|
|
end
|
|
|
|
// synthesis translate_on
|
|
|
|
endmodule
|