37 lines
1.4 KiB
Python
37 lines
1.4 KiB
Python
from migen.fhdl.structure import *
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from migen.bank.description import *
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from migen.bank import csrgen
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class ASMIprobe:
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def __init__(self, address, hub, trace_depth=16):
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self.hub = hub
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self.trace_depth = trace_depth
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slot_count = len(self.hub.get_slots())
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assert(self.trace_depth < 256)
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assert(slot_count < 256)
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self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._slot_status = [RegisterField("slot_status", 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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for i in range(slot_count)]
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self._trace = [RegisterField("trace", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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for i in range(self.trace_depth)]
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self.bank = csrgen.Bank([self._slot_count, self._trace_depth]
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+ self._slot_status + self._trace, address=address)
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def get_fragment(self):
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slots = self.hub.get_slots()
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comb = [
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self._slot_count.field.w.eq(len(slots)),
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self._trace_depth.field.w.eq(self.trace_depth)
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]
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for slot, status in zip(slots, self._slot_status):
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comb.append(status.field.w.eq(slot.state))
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shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
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for n in range(len(self._trace) - 1)]
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shift_tags.append(self._trace[-1].field.w.eq(self.hub.tag_call))
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sync = [If(self.hub.call, *shift_tags)]
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return Fragment(comb, sync) + self.bank.get_fragment()
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