litex/litex
Gabriel Somlo e451a87617 cpu/rocket: add 1-core full (fpu) wide-bus variants
- 1-core "full" (fpu-enabled) variants with double, quad mem. bus width
2022-05-10 19:35:51 -04:00
..
build gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names. 2022-05-06 16:04:24 +02:00
compat cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI). 2022-01-07 19:08:03 +01:00
gen gen/fhdl/namer: Minor cleanup to ease readability. 2022-05-09 17:53:27 +02:00
soc cpu/rocket: add 1-core full (fpu) wide-bus variants 2022-05-10 19:35:51 -04:00
tools tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug. 2022-05-10 15:16:58 +02:00
__init__.py get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed. 2021-09-28 16:27:13 +02:00