132 lines
3.2 KiB
Python
132 lines
3.2 KiB
Python
from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bus import wishbone
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from migen.genlib.misc import timeline
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from migen.genlib.record import Record
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class SpiFlash(Module):
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def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
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dummy=15, div=2):
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"""
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Simple read-only SPI flash, e.g. N25Q128 on the LX9 Microboard.
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Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
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Read). Only supports mode0 (cpol=0, cpha=0).
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`cmd` is the read instruction. Since everything is transmitted on all
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dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
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width even if dq1-dq3 are don't care during the command phase:
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For example, for N25Q128, 0xeb is the quad i/o fast read, and
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extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
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"""
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self.bus = bus = wishbone.Interface()
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##
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wbone_width = flen(bus.dat_r)
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spi_width = flen(pads.dq)
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pads.cs_n.reset = 1
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dq = TSTriple(spi_width)
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self.specials.dq = dq.get_tristate(pads.dq)
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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self.comb += [
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bus.dat_r.eq(sr[:wbone_width]),
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dq.o.eq(sr[-spi_width:]),
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]
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if div == 1:
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i = 0
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self.comb += pads.clk.eq(~ClockSignal())
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self.sync += sr.eq(Cat(dq.i, sr[:-spi_width]))
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else:
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i = Signal(max=div)
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dqi = Signal(spi_width)
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self.sync += [
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If(i == div//2 - 1,
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pads.clk.eq(1),
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dqi.eq(dq.i),
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),
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If(i == div - 1,
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i.eq(0),
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pads.clk.eq(0),
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sr.eq(Cat(dqi, sr[:-spi_width]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width//spi_width*div,
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[dq.oe.eq(1), pads.cs_n.eq(0), sr[-cmd_width:].eq(cmd)]),
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(addr_width//spi_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width//spi_width)*div,
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[dq.oe.eq(0)]),
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(1,
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[bus.ack.eq(1), pads.cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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class SpiFlashTB(Module):
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def __init__(self):
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self.submodules.master = wishbone.Initiator(self.gen_reads())
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self.pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
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self.submodules.slave = SpiFlash(self.pads)
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self.submodules.tap = wishbone.Tap(self.slave.bus)
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self.submodules.intercon = wishbone.InterconnectPointToPoint(
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self.master.bus, self.slave.bus)
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self.cycle = 0
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def gen_reads(self):
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for a in range(10):
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t = TRead(a)
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yield t
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print("read {} in {} cycles(s)".format(t.data, t.latency))
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def do_simulation(self, s):
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if s.rd(self.pads.cs_n):
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self.cycle = 0
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else:
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self.cycle += 1
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if not s.rd(self.slave.dq.oe):
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s.wr(self.slave.dq.i, self.cycle & 0xf)
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s.interrupt = self.master.done
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def _main():
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from migen.sim.generic import Simulator, TopLevel
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from migen.fhdl import verilog
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pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
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s = SpiFlash(pads)
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print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
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s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
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tb = SpiFlashTB()
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sim = Simulator(tb, TopLevel("spiflash.vcd"))
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sim.run()
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if __name__ == "__main__":
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_main()
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