47 lines
1.1 KiB
Python
47 lines
1.1 KiB
Python
from migen.fhdl.std import *
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from migen.sim.generic import *
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from misoclib.dvisampler.chansync import ChanSync
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class TB(Module):
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def __init__(self, test_seq_it):
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self.test_seq_it = test_seq_it
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self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
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self.comb += self.chansync.valid_i.eq(1)
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def do_simulation(self, s):
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try:
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de0, de1, de2 = next(self.test_seq_it)
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except StopIteration:
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s.interrupt = True
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return
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s.wr(self.chansync.data_in0.de, de0)
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s.wr(self.chansync.data_in1.de, de1)
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s.wr(self.chansync.data_in2.de, de2)
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s.wr(self.chansync.data_in0.d, s.cycle_counter)
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s.wr(self.chansync.data_in1.d, s.cycle_counter)
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s.wr(self.chansync.data_in2.d, s.cycle_counter)
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out0 = s.rd(self.chansync.data_out0.d)
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out1 = s.rd(self.chansync.data_out1.d)
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out2 = s.rd(self.chansync.data_out2.d)
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print("{0:5} {1:5} {2:5}".format(out0, out1, out2))
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def main():
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test_seq = [
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(1, 1, 1),
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(1, 1, 0),
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(0, 0, 0),
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(0, 0, 0),
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(0, 0, 1),
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(1, 1, 1),
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(1, 1, 1),
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]
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tb = TB(iter(test_seq*2))
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Simulator(tb).run()
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main()
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