vytautasb 04939990ac litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name		2019-04-08 14:07:10 +03:00
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boards	targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC	2019-03-05 13:27:11 +01:00
build	litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name	2019-04-08 14:07:10 +03:00
gen	gen/sim/core: add args support on Display	2018-12-09 09:46:10 +01:00
soc	integration/soc_zynq: fix missing SoCCore.do_finalize	2019-04-01 14:44:37 +02:00
utils	utils/litex_sim: fix main_ram_size	2019-03-16 21:25:02 +01:00
__init__.py	ease RemoteClient import	2018-09-23 10:23:00 +02:00