litex/litex
William D. Jones e558473119 Add iCEStick board. Tested with litescope. 2017-10-04 01:59:53 -04:00
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boards Add iCEStick board. Tested with litescope. 2017-10-04 01:59:53 -04:00
build Port IceStorm backend from Migen. 2017-10-03 22:48:44 -04:00
gen gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command 2017-09-13 13:47:25 +02:00
soc soc/cores: add cordic 2017-09-29 12:07:43 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00