litex/migen
Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
..
actorlib migen/actorlib/spi: apply missing CSR renaming 2015-05-13 10:17:31 +02:00
bank global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
bus bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant) 2015-06-19 08:37:16 +02:00
fhdl fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
flow global: pep8 (E302) 2015-04-13 20:45:35 +02:00
genlib migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
sim vpi: cleanup (thanks sb) 2015-05-13 10:13:14 +02:00
test add examples tests 2015-05-01 00:50:17 +08:00
util global: pep8 (E302) 2015-04-13 20:45:35 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00