605 lines
19 KiB
Verilog
605 lines
19 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_decoder.v
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// Title : Instruction decoder
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : Support for static branch prediction. Information about
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// : branch type is generated and passed on to the predictor.
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// Version : 3.2
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// : No change
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// Version : 3.3
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// : Renamed port names that conflict with keywords reserved
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// : in System-Verilog.
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// =============================================================================
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`include "lm32_include.v"
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// Index of opcode field in an instruction
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`define LM32_OPCODE_RNG 31:26
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`define LM32_OP_RNG 30:26
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// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
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`define LM32_OPCODE_ADD 5'b01101
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`define LM32_OPCODE_AND 5'b01000
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`define LM32_OPCODE_ANDHI 6'b011000
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`define LM32_OPCODE_B 6'b110000
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`define LM32_OPCODE_BI 6'b111000
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`define LM32_OPCODE_BE 6'b010001
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`define LM32_OPCODE_BG 6'b010010
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`define LM32_OPCODE_BGE 6'b010011
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`define LM32_OPCODE_BGEU 6'b010100
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`define LM32_OPCODE_BGU 6'b010101
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`define LM32_OPCODE_BNE 6'b010111
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`define LM32_OPCODE_CALL 6'b110110
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`define LM32_OPCODE_CALLI 6'b111110
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`define LM32_OPCODE_CMPE 5'b11001
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`define LM32_OPCODE_CMPG 5'b11010
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`define LM32_OPCODE_CMPGE 5'b11011
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`define LM32_OPCODE_CMPGEU 5'b11100
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`define LM32_OPCODE_CMPGU 5'b11101
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`define LM32_OPCODE_CMPNE 5'b11111
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`define LM32_OPCODE_DIVU 6'b100011
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`define LM32_OPCODE_LB 6'b000100
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`define LM32_OPCODE_LBU 6'b010000
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`define LM32_OPCODE_LH 6'b000111
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`define LM32_OPCODE_LHU 6'b001011
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`define LM32_OPCODE_LW 6'b001010
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`define LM32_OPCODE_MODU 6'b110001
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`define LM32_OPCODE_MUL 5'b00010
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`define LM32_OPCODE_NOR 5'b00001
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`define LM32_OPCODE_OR 5'b01110
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`define LM32_OPCODE_ORHI 6'b011110
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`define LM32_OPCODE_RAISE 6'b101011
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`define LM32_OPCODE_RCSR 6'b100100
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`define LM32_OPCODE_SB 6'b001100
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`define LM32_OPCODE_SEXTB 6'b101100
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`define LM32_OPCODE_SEXTH 6'b110111
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`define LM32_OPCODE_SH 6'b000011
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`define LM32_OPCODE_SL 5'b01111
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`define LM32_OPCODE_SR 5'b00101
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`define LM32_OPCODE_SRU 5'b00000
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`define LM32_OPCODE_SUB 6'b110010
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`define LM32_OPCODE_SW 6'b010110
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`define LM32_OPCODE_USER 6'b110011
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`define LM32_OPCODE_WCSR 6'b110100
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`define LM32_OPCODE_XNOR 5'b01001
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`define LM32_OPCODE_XOR 5'b00110
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_decoder (
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// ----- Inputs -------
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instruction,
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// ----- Outputs -------
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d_result_sel_0,
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d_result_sel_1,
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x_result_sel_csr,
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`ifdef LM32_MC_ARITHMETIC_ENABLED
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x_result_sel_mc_arith,
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`endif
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`ifdef LM32_NO_BARREL_SHIFT
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x_result_sel_shift,
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`endif
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`ifdef CFG_SIGN_EXTEND_ENABLED
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x_result_sel_sext,
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`endif
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x_result_sel_logic,
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`ifdef CFG_USER_ENABLED
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x_result_sel_user,
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`endif
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x_result_sel_add,
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m_result_sel_compare,
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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m_result_sel_shift,
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`endif
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w_result_sel_load,
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`ifdef CFG_PL_MULTIPLY_ENABLED
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w_result_sel_mul,
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`endif
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x_bypass_enable,
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m_bypass_enable,
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read_enable_0,
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read_idx_0,
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read_enable_1,
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read_idx_1,
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write_enable,
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write_idx,
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immediate,
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branch_offset,
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load,
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store,
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size,
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sign_extend,
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adder_op,
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logic_op,
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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direction,
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`endif
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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shift_left,
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shift_right,
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`endif
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`ifdef CFG_MC_MULTIPLY_ENABLED
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multiply,
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`endif
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`ifdef CFG_MC_DIVIDE_ENABLED
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divide,
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modulus,
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`endif
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branch,
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branch_reg,
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condition,
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bi_conditional,
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bi_unconditional,
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`ifdef CFG_DEBUG_ENABLED
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break_opcode,
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`endif
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scall,
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eret,
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`ifdef CFG_DEBUG_ENABLED
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bret,
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`endif
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`ifdef CFG_USER_ENABLED
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user_opcode,
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`endif
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csr_write_enable
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
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reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
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output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
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reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
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output x_result_sel_csr;
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reg x_result_sel_csr;
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`ifdef LM32_MC_ARITHMETIC_ENABLED
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output x_result_sel_mc_arith;
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reg x_result_sel_mc_arith;
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`endif
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`ifdef LM32_NO_BARREL_SHIFT
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output x_result_sel_shift;
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reg x_result_sel_shift;
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`endif
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`ifdef CFG_SIGN_EXTEND_ENABLED
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output x_result_sel_sext;
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reg x_result_sel_sext;
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`endif
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output x_result_sel_logic;
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reg x_result_sel_logic;
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`ifdef CFG_USER_ENABLED
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output x_result_sel_user;
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reg x_result_sel_user;
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`endif
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output x_result_sel_add;
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reg x_result_sel_add;
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output m_result_sel_compare;
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reg m_result_sel_compare;
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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output m_result_sel_shift;
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reg m_result_sel_shift;
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`endif
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output w_result_sel_load;
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reg w_result_sel_load;
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`ifdef CFG_PL_MULTIPLY_ENABLED
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output w_result_sel_mul;
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reg w_result_sel_mul;
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`endif
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output x_bypass_enable;
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wire x_bypass_enable;
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output m_bypass_enable;
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wire m_bypass_enable;
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output read_enable_0;
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wire read_enable_0;
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output [`LM32_REG_IDX_RNG] read_idx_0;
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wire [`LM32_REG_IDX_RNG] read_idx_0;
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output read_enable_1;
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wire read_enable_1;
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output [`LM32_REG_IDX_RNG] read_idx_1;
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wire [`LM32_REG_IDX_RNG] read_idx_1;
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output write_enable;
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wire write_enable;
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output [`LM32_REG_IDX_RNG] write_idx;
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wire [`LM32_REG_IDX_RNG] write_idx;
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output [`LM32_WORD_RNG] immediate;
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wire [`LM32_WORD_RNG] immediate;
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output [`LM32_PC_RNG] branch_offset;
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wire [`LM32_PC_RNG] branch_offset;
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output load;
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wire load;
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output store;
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wire store;
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output [`LM32_SIZE_RNG] size;
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wire [`LM32_SIZE_RNG] size;
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output sign_extend;
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wire sign_extend;
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output adder_op;
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wire adder_op;
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output [`LM32_LOGIC_OP_RNG] logic_op;
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wire [`LM32_LOGIC_OP_RNG] logic_op;
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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output direction;
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wire direction;
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`endif
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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output shift_left;
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wire shift_left;
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output shift_right;
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wire shift_right;
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`endif
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`ifdef CFG_MC_MULTIPLY_ENABLED
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output multiply;
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wire multiply;
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`endif
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`ifdef CFG_MC_DIVIDE_ENABLED
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output divide;
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wire divide;
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output modulus;
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wire modulus;
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`endif
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output branch;
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wire branch;
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output branch_reg;
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wire branch_reg;
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output [`LM32_CONDITION_RNG] condition;
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wire [`LM32_CONDITION_RNG] condition;
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output bi_conditional;
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wire bi_conditional;
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output bi_unconditional;
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wire bi_unconditional;
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`ifdef CFG_DEBUG_ENABLED
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output break_opcode;
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wire break_opcode;
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`endif
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output scall;
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wire scall;
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output eret;
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wire eret;
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`ifdef CFG_DEBUG_ENABLED
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output bret;
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wire bret;
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`endif
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`ifdef CFG_USER_ENABLED
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output [`LM32_USER_OPCODE_RNG] user_opcode;
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wire [`LM32_USER_OPCODE_RNG] user_opcode;
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`endif
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output csr_write_enable;
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wire csr_write_enable;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
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wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits
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wire [`LM32_WORD_RNG] call_immediate; // Call immediate
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wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
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wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
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wire select_high_immediate; // Whether to select the high immediate
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wire select_call_immediate; // Whether to select the call immediate
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Combinational logic
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/////////////////////////////////////////////////////
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// Determine opcode
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assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
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assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
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assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
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assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
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assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
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assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
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assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
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assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
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assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
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assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
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assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
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assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
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assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
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assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
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assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
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assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
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assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
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assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
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assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
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`ifdef CFG_MC_DIVIDE_ENABLED
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assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
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`endif
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assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
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assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
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assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
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assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
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assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
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`ifdef CFG_MC_DIVIDE_ENABLED
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assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
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`endif
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`ifdef LM32_MULTIPLY_ENABLED
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assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
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`endif
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assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
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assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
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assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
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assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
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assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
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assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
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`ifdef CFG_SIGN_EXTEND_ENABLED
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assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
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assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
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`endif
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assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
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`ifdef LM32_BARREL_SHIFT_ENABLED
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assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;
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`endif
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assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
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assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
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assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
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assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
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assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
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assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
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assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
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assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
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// Group opcodes by function
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assign arith = op_add | op_sub;
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assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
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assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
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assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
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assign bi_unconditional = op_bi;
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assign bra = op_b | bi_unconditional | bi_conditional;
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assign call = op_call | op_calli;
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`ifdef LM32_BARREL_SHIFT_ENABLED
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assign shift = op_sl | op_sr | op_sru;
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`endif
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`ifdef LM32_NO_BARREL_SHIFT
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assign shift = op_sr | op_sru;
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`endif
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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assign shift_left = op_sl;
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assign shift_right = op_sr | op_sru;
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`endif
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`ifdef CFG_SIGN_EXTEND_ENABLED
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assign sext = op_sextb | op_sexth;
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`endif
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`ifdef LM32_MULTIPLY_ENABLED
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assign multiply = op_mul;
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`endif
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`ifdef CFG_MC_DIVIDE_ENABLED
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assign divide = op_divu;
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assign modulus = op_modu;
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`endif
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assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
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assign store = op_sb | op_sh | op_sw;
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// Select pipeline multiplexor controls
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always @(*)
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begin
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// D stage
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if (call)
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d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
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else
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d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
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if (call)
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d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;
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else if ((instruction[31] == 1'b0) && !bra)
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d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
|
|
else
|
|
d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1;
|
|
// X stage
|
|
x_result_sel_csr = `FALSE;
|
|
`ifdef LM32_MC_ARITHMETIC_ENABLED
|
|
x_result_sel_mc_arith = `FALSE;
|
|
`endif
|
|
`ifdef LM32_NO_BARREL_SHIFT
|
|
x_result_sel_shift = `FALSE;
|
|
`endif
|
|
`ifdef CFG_SIGN_EXTEND_ENABLED
|
|
x_result_sel_sext = `FALSE;
|
|
`endif
|
|
x_result_sel_logic = `FALSE;
|
|
`ifdef CFG_USER_ENABLED
|
|
x_result_sel_user = `FALSE;
|
|
`endif
|
|
x_result_sel_add = `FALSE;
|
|
if (op_rcsr)
|
|
x_result_sel_csr = `TRUE;
|
|
`ifdef LM32_MC_ARITHMETIC_ENABLED
|
|
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
|
|
else if (shift_left | shift_right)
|
|
x_result_sel_mc_arith = `TRUE;
|
|
`endif
|
|
`ifdef CFG_MC_DIVIDE_ENABLED
|
|
else if (divide | modulus)
|
|
x_result_sel_mc_arith = `TRUE;
|
|
`endif
|
|
`ifdef CFG_MC_MULTIPLY_ENABLED
|
|
else if (multiply)
|
|
x_result_sel_mc_arith = `TRUE;
|
|
`endif
|
|
`endif
|
|
`ifdef LM32_NO_BARREL_SHIFT
|
|
else if (shift)
|
|
x_result_sel_shift = `TRUE;
|
|
`endif
|
|
`ifdef CFG_SIGN_EXTEND_ENABLED
|
|
else if (sext)
|
|
x_result_sel_sext = `TRUE;
|
|
`endif
|
|
else if (logical)
|
|
x_result_sel_logic = `TRUE;
|
|
`ifdef CFG_USER_ENABLED
|
|
else if (op_user)
|
|
x_result_sel_user = `TRUE;
|
|
`endif
|
|
else
|
|
x_result_sel_add = `TRUE;
|
|
|
|
// M stage
|
|
|
|
m_result_sel_compare = cmp;
|
|
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
|
|
m_result_sel_shift = shift;
|
|
`endif
|
|
|
|
// W stage
|
|
w_result_sel_load = load;
|
|
`ifdef CFG_PL_MULTIPLY_ENABLED
|
|
w_result_sel_mul = op_mul;
|
|
`endif
|
|
end
|
|
|
|
// Set if result is valid at end of X stage
|
|
assign x_bypass_enable = arith
|
|
| logical
|
|
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
|
|
| shift_left
|
|
| shift_right
|
|
`endif
|
|
`ifdef CFG_MC_MULTIPLY_ENABLED
|
|
| multiply
|
|
`endif
|
|
`ifdef CFG_MC_DIVIDE_ENABLED
|
|
| divide
|
|
| modulus
|
|
`endif
|
|
`ifdef LM32_NO_BARREL_SHIFT
|
|
| shift
|
|
`endif
|
|
`ifdef CFG_SIGN_EXTEND_ENABLED
|
|
| sext
|
|
`endif
|
|
`ifdef CFG_USER_ENABLED
|
|
| op_user
|
|
`endif
|
|
| op_rcsr
|
|
;
|
|
// Set if result is valid at end of M stage
|
|
assign m_bypass_enable = x_bypass_enable
|
|
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
|
|
| shift
|
|
`endif
|
|
| cmp
|
|
;
|
|
// Register file read port 0
|
|
assign read_enable_0 = ~(op_bi | op_calli);
|
|
assign read_idx_0 = instruction[25:21];
|
|
// Register file read port 1
|
|
assign read_enable_1 = ~(op_bi | op_calli | load);
|
|
assign read_idx_1 = instruction[20:16];
|
|
// Register file write port
|
|
assign write_enable = ~(bra | op_raise | store | op_wcsr);
|
|
assign write_idx = call
|
|
? 5'd29
|
|
: instruction[31] == 1'b0
|
|
? instruction[20:16]
|
|
: instruction[15:11];
|
|
|
|
// Size of load/stores
|
|
assign size = instruction[27:26];
|
|
// Whether to sign or zero extend
|
|
assign sign_extend = instruction[28];
|
|
// Set adder_op to 1 to perform a subtraction
|
|
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
|
|
// Logic operation (and, or, etc)
|
|
assign logic_op = instruction[29:26];
|
|
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
|
|
// Shift direction
|
|
assign direction = instruction[29];
|
|
`endif
|
|
// Control flow microcodes
|
|
assign branch = bra | call;
|
|
assign branch_reg = op_call | op_b;
|
|
assign condition = instruction[28:26];
|
|
`ifdef CFG_DEBUG_ENABLED
|
|
assign break_opcode = op_raise & ~instruction[2];
|
|
`endif
|
|
assign scall = op_raise & instruction[2];
|
|
assign eret = op_b & (instruction[25:21] == 5'd30);
|
|
`ifdef CFG_DEBUG_ENABLED
|
|
assign bret = op_b & (instruction[25:21] == 5'd31);
|
|
`endif
|
|
`ifdef CFG_USER_ENABLED
|
|
// Extract user opcode
|
|
assign user_opcode = instruction[10:0];
|
|
`endif
|
|
// CSR read/write
|
|
assign csr_write_enable = op_wcsr;
|
|
|
|
// Extract immediate from instruction
|
|
|
|
assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
|
|
assign select_high_immediate = op_andhi | op_orhi;
|
|
assign select_call_immediate = instruction[31];
|
|
|
|
assign high_immediate = {instruction[15:0], 16'h0000};
|
|
assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
|
|
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
|
|
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
|
|
|
|
assign immediate = select_high_immediate == `TRUE
|
|
? high_immediate
|
|
: extended_immediate;
|
|
|
|
assign branch_offset = select_call_immediate == `TRUE
|
|
? call_immediate
|
|
: branch_immediate;
|
|
|
|
endmodule
|
|
|