71 lines
2.3 KiB
Verilog
71 lines
2.3 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_functions.v
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// Title : Common functions
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.5
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// : Added function to generate log-of-two that rounds-up to
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// : power-of-two
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// =============================================================================
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function integer clogb2;
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input [31:0] value;
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begin
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for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
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value = value >> 1;
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end
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endfunction
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function integer clogb2_v1;
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input [31:0] value;
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reg [31:0] i;
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reg [31:0] temp;
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begin
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temp = 0;
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i = 0;
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for (i = 0; temp < value; i = i + 1)
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temp = 1<<i;
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clogb2_v1 = i-1;
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end
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endfunction
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