378 lines
12 KiB
Verilog
378 lines
12 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_include.v
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// Title : CPU global macros
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : No Change
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// Version : 3.2
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// : No Change
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// Version : 3.3
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// : Support for extended configuration register
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// =============================================================================
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`ifdef LM32_INCLUDE_V
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`else
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`define LM32_INCLUDE_V
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//
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// Common configuration options
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//
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`define CFG_EBA_RESET 32'h00860000
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`define CFG_DEBA_RESET 32'h10000000
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`define CFG_PL_MULTIPLY_ENABLED
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`define CFG_PL_BARREL_SHIFT_ENABLED
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`define CFG_SIGN_EXTEND_ENABLED
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`define CFG_MC_DIVIDE_ENABLED
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`define CFG_EBR_POSEDGE_REGISTER_FILE
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`define CFG_ICACHE_ENABLED
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`define CFG_ICACHE_ASSOCIATIVITY 1
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`define CFG_ICACHE_SETS 256
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`define CFG_ICACHE_BYTES_PER_LINE 16
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`define CFG_ICACHE_BASE_ADDRESS 32'h0
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`define CFG_ICACHE_LIMIT 32'h7fffffff
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`define CFG_DCACHE_ENABLED
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`define CFG_DCACHE_ASSOCIATIVITY 1
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`define CFG_DCACHE_SETS 256
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`define CFG_DCACHE_BYTES_PER_LINE 16
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`define CFG_DCACHE_BASE_ADDRESS 32'h0
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`define CFG_DCACHE_LIMIT 32'h7fffffff
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// Enable Debugging
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//`define CFG_JTAG_ENABLED
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//`define CFG_JTAG_UART_ENABLED
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//`define CFG_DEBUG_ENABLED
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//`define CFG_HW_DEBUG_ENABLED
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//`define CFG_ROM_DEBUG_ENABLED
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//`define CFG_BREAKPOINTS 32'h4
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//`define CFG_WATCHPOINTS 32'h4
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//`define CFG_EXTERNAL_BREAK_ENABLED
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//`define CFG_GDBSTUB_ENABLED
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//
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// End of common configuration options
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//
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`ifdef TRUE
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`else
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`define TRUE 1'b1
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`define FALSE 1'b0
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`define TRUE_N 1'b0
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`define FALSE_N 1'b1
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`endif
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// Wishbone configuration
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`define CFG_IWB_ENABLED
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`define CFG_DWB_ENABLED
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// Data-path width
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`define LM32_WORD_WIDTH 32
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`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
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`define LM32_SHIFT_WIDTH 5
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`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
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`define LM32_BYTE_SELECT_WIDTH 4
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`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
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// Register file size
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`define LM32_REGISTERS 32
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`define LM32_REG_IDX_WIDTH 5
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`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
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// Standard register numbers
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`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
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`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
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`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
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// Range of Program Counter. Two LSBs are always 0.
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`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
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`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
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// Range of an instruction
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`define LM32_INSTRUCTION_WIDTH 32
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`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
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// Adder operation
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`define LM32_ADDER_OP_ADD 1'b0
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`define LM32_ADDER_OP_SUBTRACT 1'b1
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// Shift direction
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`define LM32_SHIFT_OP_RIGHT 1'b0
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`define LM32_SHIFT_OP_LEFT 1'b1
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// Bus errors
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`define CFG_BUS_ERRORS_ENABLED
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// Derive macro that indicates whether we have single-stepping or not
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`ifdef CFG_ROM_DEBUG_ENABLED
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`define LM32_SINGLE_STEP_ENABLED
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`else
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`ifdef CFG_HW_DEBUG_ENABLED
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`define LM32_SINGLE_STEP_ENABLED
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`endif
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`endif
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// Derive macro that indicates whether JTAG interface is required
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`ifdef CFG_JTAG_UART_ENABLED
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`define LM32_JTAG_ENABLED
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`else
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_JTAG_ENABLED
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`else
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`endif
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`endif
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// Derive macro that indicates whether ROM debug is required
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`ifdef CFG_GDBSTUB_ENABLED
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`define CFG_ROM_DEBUG_ENABLED
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`endif
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// Derive macro that indicates whether we have a barrel-shifter or not
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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`define LM32_BARREL_SHIFT_ENABLED
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`else // CFG_PL_BARREL_SHIFT_ENABLED
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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`define LM32_BARREL_SHIFT_ENABLED
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`else
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`define LM32_NO_BARREL_SHIFT
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`endif
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`endif // CFG_PL_BARREL_SHIFT_ENABLED
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// Derive macro that indicates whether we have a multiplier or not
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`ifdef CFG_PL_MULTIPLY_ENABLED
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`define LM32_MULTIPLY_ENABLED
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`else
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`ifdef CFG_MC_MULTIPLY_ENABLED
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`define LM32_MULTIPLY_ENABLED
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`endif
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`endif
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// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
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`ifdef CFG_MC_DIVIDE_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
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`endif
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`ifdef CFG_MC_MULTIPLY_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
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`endif
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
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`endif
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// Derive macro that indicates if we are using an EBR register file
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`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
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`define LM32_EBR_REGISTER_FILE
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`endif
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`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
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`define LM32_EBR_REGISTER_FILE
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`endif
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// Revision number
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`define LM32_REVISION 6'h02
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// Logical operations - Function encoded directly in instruction
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`define LM32_LOGIC_OP_RNG 3:0
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// Conditions for conditional branches
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`define LM32_CONDITION_WIDTH 3
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`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
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`define LM32_CONDITION_E 3'b001
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`define LM32_CONDITION_G 3'b010
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`define LM32_CONDITION_GE 3'b011
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`define LM32_CONDITION_GEU 3'b100
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`define LM32_CONDITION_GU 3'b101
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`define LM32_CONDITION_NE 3'b111
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`define LM32_CONDITION_U1 3'b000
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`define LM32_CONDITION_U2 3'b110
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// Size of load or store instruction - Encoding corresponds to opcode
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`define LM32_SIZE_WIDTH 2
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`define LM32_SIZE_RNG 1:0
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`define LM32_SIZE_BYTE 2'b00
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`define LM32_SIZE_HWORD 2'b11
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`define LM32_SIZE_WORD 2'b10
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`define LM32_ADDRESS_LSBS_WIDTH 2
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// Width and range of a CSR index
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_CSR_WIDTH 5
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`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
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`else
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`ifdef CFG_JTAG_ENABLED
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`define LM32_CSR_WIDTH 4
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`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
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`else
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`define LM32_CSR_WIDTH 3
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`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
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`endif
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`endif
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// CSR indices
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`define LM32_CSR_IE `LM32_CSR_WIDTH'h0
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`define LM32_CSR_IM `LM32_CSR_WIDTH'h1
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`define LM32_CSR_IP `LM32_CSR_WIDTH'h2
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`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
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`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
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`define LM32_CSR_CC `LM32_CSR_WIDTH'h5
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`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
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`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_CSR_DC `LM32_CSR_WIDTH'h8
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`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
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`endif
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`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
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`ifdef CFG_JTAG_ENABLED
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`define LM32_CSR_JTX `LM32_CSR_WIDTH'he
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`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
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`endif
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
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`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
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`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
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`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
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`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
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`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
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`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
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`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
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`endif
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// Values for WPC CSR
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`define LM32_WPC_C_RNG 1:0
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`define LM32_WPC_C_DISABLED 2'b00
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`define LM32_WPC_C_READ 2'b01
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`define LM32_WPC_C_WRITE 2'b10
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`define LM32_WPC_C_READ_WRITE 2'b11
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// Exception IDs
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`define LM32_EID_WIDTH 3
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`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
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`define LM32_EID_RESET 3'h0
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`define LM32_EID_BREAKPOINT 3'd1
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`define LM32_EID_INST_BUS_ERROR 3'h2
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`define LM32_EID_WATCHPOINT 3'd3
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`define LM32_EID_DATA_BUS_ERROR 3'h4
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`define LM32_EID_DIVIDE_BY_ZERO 3'h5
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`define LM32_EID_INTERRUPT 3'h6
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`define LM32_EID_SCALL 3'h7
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// Pipeline result selection mux controls
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`define LM32_D_RESULT_SEL_0_RNG 0:0
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`define LM32_D_RESULT_SEL_0_REG_0 1'b0
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`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
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`define LM32_D_RESULT_SEL_1_RNG 1:0
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`define LM32_D_RESULT_SEL_1_ZERO 2'b00
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`define LM32_D_RESULT_SEL_1_REG_1 2'b01
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`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
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`define LM32_USER_OPCODE_WIDTH 11
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`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
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// Derive a macro to indicate if either of the caches are implemented
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`ifdef CFG_ICACHE_ENABLED
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`define LM32_CACHE_ENABLED
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`else
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`ifdef CFG_DCACHE_ENABLED
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`define LM32_CACHE_ENABLED
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`endif
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`endif
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/////////////////////////////////////////////////////
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// Interrupts
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/////////////////////////////////////////////////////
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// Always enable interrupts
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`define CFG_INTERRUPTS_ENABLED
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// Currently this is fixed to 32 and should not be changed
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`define CFG_INTERRUPTS 32
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`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
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`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
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/////////////////////////////////////////////////////
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// General
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/////////////////////////////////////////////////////
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// Sub-word range types
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`define LM32_BYTE_WIDTH 8
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`define LM32_BYTE_RNG 7:0
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`define LM32_HWORD_WIDTH 16
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`define LM32_HWORD_RNG 15:0
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// Word sub-byte indicies
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`define LM32_BYTE_0_RNG 7:0
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`define LM32_BYTE_1_RNG 15:8
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`define LM32_BYTE_2_RNG 23:16
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`define LM32_BYTE_3_RNG 31:24
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// Word sub-halfword indices
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`define LM32_HWORD_0_RNG 15:0
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`define LM32_HWORD_1_RNG 31:16
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// Use a synchronous reset
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`define CFG_RESET_SENSITIVITY
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// Wishbone defines
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// Refer to Wishbone System-on-Chip Interconnection Architecture
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// These should probably be moved to a Wishbone common file
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// Wishbone cycle types
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`define LM32_CTYPE_WIDTH 3
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`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
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`define LM32_CTYPE_CLASSIC 3'b000
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`define LM32_CTYPE_CONSTANT 3'b001
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`define LM32_CTYPE_INCREMENTING 3'b010
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`define LM32_CTYPE_END 3'b111
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// Wishbone burst types
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`define LM32_BTYPE_WIDTH 2
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`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
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`define LM32_BTYPE_LINEAR 2'b00
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`define LM32_BTYPE_4_BEAT 2'b01
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`define LM32_BTYPE_8_BEAT 2'b10
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`define LM32_BTYPE_16_BEAT 2'b11
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`endif
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